PIC32MX230F128L-I/PF View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX230F128L-I/PF

32-bit Microcontrollers (up to 512 KB Flash and 64 KB SRAM) with Audio/Graphics/Touch (HMI), CAN, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY

REGISTER 21-2: RTCALRM: RTC ALARM CONTROL REGISTER

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

31:24

23:16

15:8

7:0

U-0

—

U-0

—

R/W-0

ALRMEN(1,2)

R/W-0

U-0

—

U-0

—

R/W-0

CHIME(2)

R/W-0

U-0

—

U-0

—

R/W-0

PIV(2)

R/W-0

U-0

U-0

—

—

U-0

U-0

—

—

R-0

ALRMSYNC(3)

R/W-0

R/W-0

R/W-0

ARPT<7:0>(3)

U-0

U-0

—

—

U-0

U-0

—

—

R/W-0

R/W-0

AMASK<3:0>(3)

R/W-0

R/W-0

Bit

24/16/8/0

U-0

—

U-0

—

R/W-0

R/W-0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ALRMEN: Alarm Enable bit(1,2)

1 = Alarm is enabled

0 = Alarm is disabled

bit 14 CHIME: Chime Enable bit(2)

1 = Chime is enabled – ARPT<7:0> is allowed to rollover from 0x00 to 0xFF

0 = Chime is disabled – ARPT<7:0> stops once it reaches 0x00

bit 13 PIV: Alarm Pulse Initial Value bit(2)

When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse.

When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse.

bit 12 ALRMSYNC: Alarm Sync bit(3)

1 = ARPT<7:0> and ALRMEN may change as a result of a half second rollover during a read. 

The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple

bits may be changing, which are then synchronized to the PB clock domain

0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because the prescaler is > 32 RTC

clocks away from a half-second rollover

bit 11-8 AMASK<3:0>: Alarm Mask Configuration bits(3)

0000 = Every half-second

0001 = Every second

0010 = Every 10 seconds

0011 = Every minute

0100 = Every 10 minutes

0101 = Every hour

0110 = Once a day

0111 = Once a week

1000 = Once a month

1001 = Once a year (except when configured for February 29, once every four years)

1010 = Reserved; do not use

1011 = Reserved; do not use

11xx = Reserved; do not use

Note 1:

2:

3:

Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and

CHIME = 0.

This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.

This assumes a CPU read will execute in less than 32 PBCLKs.

Note: This register is reset only on a Power-on Reset (POR).

 2014-2017 Microchip Technology Inc.

DS60001290E-page 225

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