TABLE 23-1: CAN1 REGISTER SUMMARY (CONTINUED)
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
B340
C1FIFOBA
31:16
15:0
C1FIFOBA<31:0>
0000
0000
B350
C1FIFOCONn 31:16
(n = 0-15) 15:0
—
—
—
FRESET
—
UINC
—
DONLY
—
—
—
—
—
—
—
—
—
—
FSIZE<4:0>
0000
—
TXEN TXABAT TXLARB TXERR TXREQ RTREN
TXPRI<1:0>
0000
B360
C1FIFOINTn 31:16
(n = 0-15) 15:0
—
—
—
—
—
—
—
—
— TXNFULLIE TXHALFIE TXEMPTYIE —
— TXNFULLIF TXHALFIF TXEMPTYIF —
—
—
—
—
—
RXOVFLIE
RXFULLIE
RXHALFIE
RXN
EMPTYIE
0000
—
RXOVFLIF
RXFULLIF
RXHALFIF
RXN
EMPTYIF
0000
B370
C1FIFOUAn 31:16
(n = 0-15) 15:0
C1FIFOUA<31:0>
0000
0000
B380
C1FIFOCIn 31:16
(n = 0-15) 15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— 0000
—
—
—
C1FIFOCIn<4:0>
0000
Legend:
Note 1:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET, and INV Registers” for more
information.