PIC32MX1XX/2XX/5XX 64/100-PIN FAMILY
FIGURE 8-2:
PIC32MX1XX/2XX/5XX PLL BLOCK DIAGRAM
FIN:(1)
FSYS:(1)
3.92 MHz FIN z 60 MHz FSYS z
SYSCLK:(1)
234,375 Hz SYSCLK
50 MHz
(Crystal, External Clock
Or Internal RC)
FPLLIDIV
X
VCO
FPLLODIV
SYSCLK
Divide By:
1,2,3,4,5,6,10,12
FPLLMULT
Divide By:
1,2,4,8,16,32,64,256
Multiply By:
15,16,17,18,19,
20,21,22,23,24
Note 1: This frequency range must be satisfied at all times if the PLL is enabled and software is updating the
corresponding bits in the OSCON register.
2014-2017 Microchip Technology Inc.
DS60001290E-page 75