8.1 Control Registers
TABLE 8-1: OSCILLATOR CONFIGURATION REGISTER MAP
Bits
31/15 30/14 29/13
28/12 27/11 26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
F000 OSCCON 31:16 —
15:0 —
—
PLLODIV<2:0>
COSC<2:0>
—
FRCDIV<2:0>
NOSC<2:0>
— SOSCRDY PBDIVRDY PBDIV<1:0>
CLKLOCK ULOCK SLOCK SLPEN
CF
PLLMULT<2:0>
x1xx(2)
UFRCEN(3) SOSCEN OSWEN xxxx(2)
F010 OSCTUN 31:16 —
—
—
15:0 —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TUN<5:0>
—
—
0000
0000
31:16 —
F020 REFOCON 15:0 ON
—
SIDL
RODIV<14:0>
OE
RSLP
— DIVSWEN ACTIVE
—
—
—
—
ROSEL<3:0>
0000
0000
31:16
F030 REFOTRIM 15:0
—
—
—
ROTRIM<8:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
2:
3:
With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2
“CLR, SET, and INV Registers” for more information.
Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
This bit is only available on devices with a USB module.