STLC5460 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STLC5460 Datasheet PDF : 54 Pages
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STLC5460
CLOCK TIMING
Synchronization signals delivered by the system
t5h t5l
t1
t2
PDC
3
4
5
6
7
0
1
t3
t4
PFS
TXD0/3
Bit3
Bit4
Bit5
TS0/3
RXD0/3
Bit6
Bit7
Bit0
Bit1
t6
t7 t8
TDM0/3
FSC delivered
by the circuit
Time Slot 31
Time Slot 0
DEL, ISPP and PFSP bits of PCM Configuration Register are at zero (no delay))
Clocks received by the LCIC
tx
t1=1/f1
t2
t3
t4
t5
t6
t7
t8
Parameter
Clock Period if f1 = 16384KHz
Clock Period if f1 = 8192KHz
Clock Period if f1 = 4096KHz
Bit-time if f1 = 16384KHz
Bit-time if f1 = 8192KHz
Bit-time if f1 = 4096KHz
Set up time PFS/PDC
Hold time PFS/PDC
Clock ratio t5h/t5l
PDC to data 50pF
PDC to data 100pF
Set up time data/DCL
Hold time data/DCL
T min. T typ. T max. Unit
60
61
62
ns
120
122
124
ns
239
244
249
ns
122
ns
244
ns
488
ns
20
t1-20
ns
20
12500-t1 ns
75
100
125
%
50
ns
100
ns
20
ns
20
ns
36/54
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