STLC5460 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STLC5460 Datasheet PDF : 54 Pages
| |||
CLOCK TIMING
TDM synchronization
STLC5460
PDC received by
the LCIC
t2
DCL delivered by
the LCIC
t1
t3
t4
FSC delivered by
the LCIC
DOUT 0/1
DIN 0/1
t5
t6
Bit7, Time Slot 31
Bit0, Time Slot 0
t7 t8
The four Multiplex Configuration Registers are at zero (no delay between FSC and Multiplexes)
Clocks delivered by the LCIC
tx
Parameter
t1
Clock Period if 4096KHz
Clock Period if 2048KHz
t2
Delay between PDC and DCL (30pF)
t3
Delay between DCL and rising edge FSC (30pF)
t4
Delay between DCL and falling edge FSC (30pF)
t5
Duration FSC
t6
DCL to data 50pF
DCL to data 100pF
t7
Set up time data/DCL
t8
Hold time data/DCL
T min. T typ. T max. Unit
Id PDC 244 Id PDC
ns
488
ns
5
30
ns
30
ns
30
ns
488
ns
50
ns
100
ns
20
ns
20
ns
37/54
Share Link: 