DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—
12.6
12.7
12.5.8 Message Control Register eXtension (MCRX) (SB_ADDR_EXTN_REG)—Offset
D8h .................................................................................................... 132
12.5.9 Manufacturer ID (PCI_MANUFACTURER)—Offset F8h ................................. 133
IO Mapped Register ......................................................................................... 134
12.6.1 ACPI Processor Block............................................................................. 134
12.6.1.1 Processor Control (P_CNT)—Offset 0h ........................................ 134
12.6.1.2 Level 2 Register (P_LVL2)—Offset 4h ......................................... 135
12.6.1.3 C6 Control Register (P_C6C)—Offset Ch ..................................... 135
12.6.2 SPI DMA Block ..................................................................................... 136
12.6.2.1 SPI DMA Count Register (SPI_DMA_CNT_IOSF)—Offset 0h ........... 136
12.6.2.2 SPI DMA Destination Register (SPI_DMA_DST_IOSF)—Offset 4h .... 136
12.6.2.3 SPI DMA Source Register (SPI_DMA_SRC_IOSF)—Offset 8h .......... 137
Message Bus Register....................................................................................... 138
12.7.1 Host Bridge Arbiter (Port 0x00) .............................................................. 138
12.7.1.1 Enhanced Configuration Space (AEC_CTRL)—Offset 0h ................. 138
12.7.1.2 STATUS—Offset 21h ................................................................ 138
12.7.1.3 Requester ID Match Control (ASUBCHAN_CTRL)—Offset 50h ......... 139
12.7.1.4 Requester ID Match Sub-Channel 1 (ASUBCHAN1_MATCH)—Offset
51h ....................................................................................... 140
12.7.1.5 Requester ID Match Sub-Channel 2 (ASUBCHAN2_MATCH)—Offset
52h ....................................................................................... 141
12.7.1.6 Requester ID Match Sub-Channel 3 (ASUBCHAN3_MATCH)—Offset
53h ....................................................................................... 141
12.7.2 Host Bridge (Port 0x03) ......................................................................... 142
12.7.2.1 Host Miscellaneous Controls 2 (HMISC2)—Offset 3h ..................... 143
12.7.2.2 Host System Management Mode Controls (HSMMCTL)—Offset 4h... 144
12.7.2.3 Host Memory I/O Boundary (HMBOUND)—Offset 8h ..................... 145
12.7.2.4 Extended Configuration Space (HECREG)—Offset 9h .................... 146
12.7.2.5 Host Bridge Write Flush Control (HWFLUSH)—Offset Ch ................ 147
12.7.2.6 MTRR Capabilities (MTRR_CAP)—Offset 40h ................................ 147
12.7.2.7 MTRR Default Type (MTRR_DEF_TYPE)—Offset 41h...................... 148
12.7.2.8 MTRR Fixed 64KB Range 0x00000 (MTRR_FIX64K_00000)—Offset
42h ....................................................................................... 148
12.7.2.9 MTRR Fixed 64KB Range 0x40000 (MTRR_FIX64K_40000)—Offset
43h ....................................................................................... 149
12.7.2.10MTRR Fixed 16KB Range 0x80000 (MTRR_FIX16K_80000)—Offset
44h ....................................................................................... 149
12.7.2.11MTRR Fixed 16KB Range 0x90000 (MTRR_FIX16K_90000)—Offset
45h ....................................................................................... 150
12.7.2.12MTRR Fixed 16KB Range 0xA0000 (MTRR_FIX16K_A0000)—Offset
46h ....................................................................................... 151
12.7.2.13MTRR Fixed 16KB Range 0xB0000 (MTRR_FIX16K_B0000)—Offset
47h ....................................................................................... 151
12.7.2.14MTRR Fixed 4KB Range 0xC0000 (MTRR_FIX4K_C0000)—Offset
48h ....................................................................................... 152
12.7.2.15MTRR Fixed 4KB Range 0xC4000 (MTRR_FIX4K_C4000)—Offset
49h ....................................................................................... 152
12.7.2.16MTRR Fixed 4KB Range 0xC8000 (MTRR_FIX4K_C8000)—Offset
4Ah ....................................................................................... 153
12.7.2.17MTRR Fixed 4KB Range 0xCC000 (MTRR_FIX4K_CC000)—Offset
4Bh ....................................................................................... 153
12.7.2.18MTRR Fixed 4KB Range 0xD0000 (MTRR_FIX4K_D0000)—Offset
4Ch ....................................................................................... 154
12.7.2.19MTRR Fixed 4KB Range 0xD40000 (MTRR_FIX4K_D4000)—Offset
4Dh....................................................................................... 155
12.7.2.20MTRR Fixed 4KB Range 0xD8000 (MTRR_FIX4K_D8000)—Offset
4Eh ....................................................................................... 155
12.7.2.21MTRR Fixed 4KB Range 0xDC000 (MTRR_FIX4K_DC000)—Offset
4Fh ....................................................................................... 156
Intel® Quark SoC X1000
DS
6
October 2013
Document Number: 329676-001US
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