DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
Part Name
Description
Manufacturer
DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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Intel® Quark SoC X1000—
12.7.3.7 Watchdog Control Register (P_CFG_74)—Offset 74h .................... 175
12.7.3.8 ECC Scrubber Start Address Register (P_CFG_76)—Offset 76h ...... 176
12.7.3.9 ECC Scrubber End Address Register (P_CFG_77)—Offset 77h ........ 176
12.7.3.10ECC Scrubber Next Address Register (P_CFG_7C)—Offset 7Ch ...... 177
12.7.3.11Thermal Sensor Mode Register (P_CFG_B0)—Offset B0h............... 178
12.7.3.12Thermal Sensor Temperature Register (P_CFG_B1)—Offset B1h .... 178
12.7.3.13Thermal Sensor Programmable Trip Point Register
(P_CFG_B2)—Offset B2h .......................................................... 179
12.7.4 Memory Manager (Port 0x05) ................................................................. 180
12.7.4.1 Control (BCTRL)—Offset 1h ...................................................... 181
12.7.4.2 Write Flush Policy (BWFLUSH)—Offset 2h ................................... 182
12.7.4.3 Isolated Memory Region Violation Control (BIMRVCTL)—Offset 19h 183
12.7.4.4 Debug 1 (DEBUG1)—Offset 31h ................................................ 184
12.7.4.5 Isolated Memory Region 0 Low Address (IMR0L)—Offset 40h ........ 185
12.7.4.6 Isolated Memory Region 0 High Address (IMR0H)—Offset 41h ....... 186
12.7.4.7 Isolated Memory Region 0 Read Mask (IMR0RM)—Offset 42h ........ 186
12.7.4.8 Isolated Memory Region 0 Write Mask (IMR0WM)—Offset 43h ....... 188
12.7.4.9 Isolated Memory Region 1 Low Address (IMR1L)—Offset 44h ........ 190
12.7.4.10Isolated Memory Region 1 High Address (IMR1H)—Offset 45h ....... 191
12.7.4.11Isolated Memory Region 1 Read Mask (IMR1RM)—Offset 46h ........ 191
12.7.4.12Isolated Memory Region 1 Write Mask (IMR1WM)—Offset 47h ....... 193
12.7.4.13Isolated Memory Region 2 Low Address (IMR2L)—Offset 48h ........ 195
12.7.4.14Isolated Memory Region 2 High Address (IMR2H)—Offset 49h ....... 195
12.7.4.15Isolated Memory Region 2 Read Mask (IMR2RM)—Offset 4Ah ........ 196
12.7.4.16Isolated Memory Region 2 Write Mask (IMR2WM)—Offset 4Bh....... 198
12.7.4.17Isolated Memory Region 3 Low Address (IMR3L)—Offset 4Ch ........ 199
12.7.4.18Isolated Memory Region 3 High Address (IMR3H)—Offset 4Dh....... 200
12.7.4.19Isolated Memory Region 3 Read Mask (IMR3RM)—Offset 4Eh ........ 200
12.7.4.20Isolated Memory Region 3 Write Mask (IMR3WM)—Offset 4Fh ....... 202
12.7.4.21Isolated Memory Region 4 Low Address (IMR4L)—Offset 50h ........ 204
12.7.4.22Isolated Memory Region 4 High Address (IMR4H)—Offset 51h ....... 205
12.7.4.23Isolated Memory Region 4 Read Mask (IMR4RM)—Offset 52h ........ 205
12.7.4.24Isolated Memory Region 4 Write Mask (IMR4WM)—Offset 53h ....... 207
12.7.4.25Isolated Memory Region 5 Low Address (IMR5L)—Offset 54h ........ 209
12.7.4.26Isolated Memory Region 5 High Address (IMR5H)—Offset 55h ....... 209
12.7.4.27Isolated Memory Region 5 Read Mask (IMR5RM)—Offset 56h ........ 210
12.7.4.28Isolated Memory Region 5 Write Mask (IMR5WM)—Offset 57h ....... 212
12.7.4.29Isolated Memory Region 6 Low Address (IMR6L)—Offset 58h ........ 213
12.7.4.30Isolated Memory Region 6 High Address (IMR6H)—Offset 59h ....... 214
12.7.4.31Isolated Memory Region 6 Read Mask (IMR6RM)—Offset 5Ah ........ 214
12.7.4.32Isolated Memory Region 6 Write Mask (IMR6WM)—Offset 5Bh....... 216
12.7.4.33Isolated Memory Region 7 Low Address (IMR7L)—Offset 5Ch ........ 218
12.7.4.34Isolated Memory Region 7 High Address (IMR7H)—Offset 5Dh....... 219
12.7.4.35Isolated Memory Region 7 Read Mask (IMR7RM)—Offset 5Eh ........ 219
12.7.4.36Isolated Memory Region 7 Write Mask (IMR7WM)—Offset 5Fh ....... 221
12.7.4.37eSRAM Control (ESRAMCTRL)—Offset 81h .................................. 223
12.7.4.38eSRAM Block Page Control (ESRAMPGCTRL_BLOCK)—Offset 82h ... 224
12.7.4.39eSRAM Correctable Error (ESRAMCERR)—Offset 83h .................... 225
12.7.4.40eSRAM Uncorrectable Error (ESRAMUERR)—Offset 84h................. 226
12.7.4.41eSRAM ECC Error Syndrome (ESRAMSDROME)—Offset 88h........... 227
12.7.5 Memory Manager eSRAM (Port 0x05) ...................................................... 228
12.7.5.1 eSRAM Page Control Register[0-127]
(ESRAMPGCTRL[0-127])—Offset 0h, Count 128, Stride 4h ............ 228
12.7.6 SoC Unit (Port 0x31) ............................................................................. 229
12.7.6.1 Thermal Sensor Configuration 4 (SCU_TSCFG4_Config)—Offset
34h ....................................................................................... 229
12.7.6.2 Sticky Write Once (CFGSTICKY_W1)—Offset 50h ......................... 230
12.7.6.3 Sticky Read/Write (CFGSTICKY_RW)—Offset 51h......................... 230
12.7.6.4 Non-Sticky Read/Write Once (CFGNONSTICKY_W1)—Offset 52h.... 231
Intel® Quark SoC X1000
DS
8
October 2013
Document Number: 329676-001US
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