DHQ1ECCSECETS1SR1WH View Datasheet(PDF) - Intel
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DHQ1ECCSECETS1SR1WH Datasheet PDF : 921 Pages
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—Intel® Quark SoC X1000
13.0 System Memory Controller .................................................................................... 233
13.1 Signal Descriptions .......................................................................................... 233
13.2 Features ........................................................................................................ 234
13.2.1 System Memory Technology Supported ................................................... 234
13.2.2 Rules for Populating Memory Down Ranks................................................ 235
13.2.3 DRAM Error Detection & Correction (EDC)................................................ 235
13.2.4 DRAM Data Scrambling ......................................................................... 235
13.2.5 Power Management .............................................................................. 235
13.3 Register Map .................................................................................................. 235
13.4 Message Bus Registers..................................................................................... 236
13.4.1 DRAM Rank Population (DRP)—Offset 0h ................................................. 237
13.4.2 DRAM Timing Register 0 (DTR0)—Offset 1h ............................................. 238
13.4.3 DRAM Timing Register 1 (DTR1)—Offset 2h ............................................. 240
13.4.4 DRAM Timing Register 2 (DTR2)—Offset 3h ............................................. 242
13.4.5 DRAM Timing Register 3 (DTR3)—Offset 4h ............................................. 243
13.4.6 DRAM Timing Register 4 (DTR4)—Offset 5h ............................................. 244
13.4.7 DRAM Power Management Control 0 (DPMC0)—Offset 6h........................... 245
13.4.8 DRAM Refresh Control (DRFC)—Offset 8h ................................................ 247
13.4.9 DRAM Scheduler Control (DSCH)—Offset 9h............................................. 248
13.4.10DRAM Calibration Control (DCAL)—Offset Ah ............................................ 249
13.4.11DRAM Reset Management Control (DRMC)—Offset Bh ............................... 250
13.4.12Power Management Status (PMSTS)—Offset Ch ........................................ 251
13.4.13DRAM Control Operation (DCO)—Offset Fh............................................... 252
13.4.14Sticky Scratchpad 0 (SSKPD0)—Offset 4Ah .............................................. 252
13.4.15Sticky Scratchpad 1 (SSKPD1)—Offset 4Bh .............................................. 253
13.4.16DRAM ECC Control Register (DECCCTRL)—Offset 60h ................................ 253
13.4.17DRAM ECC Status (DECCSTAT)—Offset 61h ............................................. 254
13.4.18DRAM ECC Single Bit Error Count (DECCSBECNT)—Offset 62h .................... 254
13.4.19DRAM Single Bit ECC Error Captured Address (DECCSBECA)—Offset 68h ..... 255
13.4.20DRAM Single Bit ECC Error Captured Syndrome (DECCSBECS)—Offset 69h .. 256
13.4.21DRAM Double Bit ECC Error Captured Address (DECCDBECA)—Offset 6Ah .... 256
13.4.22DRAM Double Bit ECC Error Captured Syndrome (DECCDBECS)—Offset 6Bh. 257
13.4.23Memory Controller Fuse Status (DFUSESTAT)—Offset 70h ......................... 257
13.4.24Scrambler Seed (DSCRMSEED)—Offset 80h ............................................. 258
14.0 PCI Express* 2.0 ................................................................................................... 259
14.1 Signal Descriptions .......................................................................................... 259
14.2 Features ........................................................................................................ 259
14.2.1 Interrupts and Events ........................................................................... 260
14.2.1.1 Express Card Hot Plug Events ................................................... 260
14.2.1.2 System Error (SERR)............................................................... 261
14.2.2 Power Management .............................................................................. 261
14.3 References ..................................................................................................... 261
14.4 Register Map .................................................................................................. 261
14.5 PCI Configuration Registers .............................................................................. 262
14.5.1 Identifiers (ID)—Offset 0h ..................................................................... 264
14.5.2 Primary Status (CMD_PSTS)—Offset 4h................................................... 264
14.5.3 Class Code (RID_CC)—Offset 8h............................................................. 266
14.5.4 Header Type (CLS_PLT_HTYPE)—Offset Ch .............................................. 266
14.5.5 Secondary Latency Timer (BNUM_SLT)—Offset 18h .................................. 267
14.5.6 Secondary Status (IOBL_SSTS)—Offset 1Ch ............................................ 267
14.5.7 Memory Base and Limit (MBL)—Offset 20h .............................................. 268
14.5.8 Prefetchable Memory Base and Limit (PMBL)—Offset 24h........................... 269
14.5.9 Prefetchable Memory Base Upper 32 Bits (PMBU32)—Offset 28h ................. 269
14.5.10Prefetchable Memory Limit Upper 32 Bits (PMLU32)—Offset 2Ch ................. 270
October 2013
Document Number: 329676-001US
Intel® Quark SoC X1000
DS
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