AT90PWM2(2005) View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT90PWM2
(Rev.:2005)

8-bit Microcontroller with 8K Bytes In-System Programmable Flash

Atmel Corporation 

AT90PWM2/3

Ports as General Digital

I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 25 shows a

functional description of one I/O-port pin, here generically called Pxn.

Figure 25. General Digital I/O(1)

Configuring the Pin

QD

DDxn

Q CLR

RESET

PUD

WDx

RDx

1

Pxn

QD

PORTxn

0

SLEEP

Q CLR

RESET

RRx

WPx

WRx

SYNCHRONIZER

DQ

LQ

DQ

PINxn

Q

RPx

clk I/O

PUD: PULLUP DISABLE

SLEEP: SLEEP CONTROL

clkI/O : I/O CLOCK

WDx: WRITE DDRx

RDx: READ DDRx

WRx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

WPx: WRITE PINx REGISTER

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.

clkI/O, SLEEP, and PUD are common to all ports.

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in

“Register Description for I/O-Ports” on page 80, the DDxn bits are accessed at the

DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at

the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written

logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is config-

ured as an input pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up

resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic

zero or the pin has to be configured as an output pin

The port pins are tri-stated when reset condition becomes active, even if no clocks are

running.

63

4317B–AVR–02/05

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