AT90PWM2(2005) View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT90PWM2
(Rev.:2005)

8-bit Microcontroller with 8K Bytes In-System Programmable Flash

Atmel Corporation 

Consider the clock period starting shortly after the first falling edge of the system clock.

The latch is closed when the clock is low, and goes transparent when the clock is high,

as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is

latched when the system clock goes low. It is clocked into the PINxn Register at the suc-

ceeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single

signal transition on the pin will be delayed between ½ and 1½ system clock period

depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as

indicated in Figure 27. The out instruction sets the “SYNC LATCH” signal at the positive

edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock

period.

Figure 27. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

r16

0xFF

INSTRUCTIONS

out PORTx, r16

nop

in r17, PINx

SYNC LATCH

PINxn

r17

0x00

t pd

0xFF

66 AT90PWM2/3

4317B–AVR–02/05

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