AT90PWM2B-16SU View Datasheet(PDF) - Atmel Corporation

Part Name

Description

Manufacturer

AT90PWM2B-16SU

8-bit Atmel Microcontroller with 8K Bytes In-System Programmable Flash

Atmel Corporation 

AT90PWM2/3/2B/3B

Table 21-7. ADC Auto Trigger Source Selection for amplified conversions

ADTS3

1

ADTS2

0

ADTS1

1

ADTS0

0

Description

PSC2ASY Event(1)

1

0

1

1

Reserved

1

1

0

0

Reserved

1

1

0

1

Reserved

1

1

1

0

Reserved

1

1

1

1

Reserved

1.

For trigger on any PSC event, if the PSC uses the PLL clock, the core must use PLL/4 clock

source.

21.8.4

ADC Result Data Registers – ADCH and ADCL

When an ADC conversion is complete, the conversion results are stored in these two result data

registers.

When the ADCL register is read, the two ADC result data registers can’t be updated until the

ADCH register has also been read.

Consequently, in 10-bit configuration, the ADCL register must be read first before the ADCH.

Nevertheless, to work easily with only 8-bit precision, there is the possibility to left adjust the

result thanks to the ADLAR bit in the ADCSRA register. Like this, it is sufficient to only read

ADCH to have the conversion result.

21.8.4.1

ADLAR = 0

Bit

Read/Write

Initial Value

7

-

ADC7

R

R

0

0

6

-

ADC6

R

R

0

0

5

-

ADC5

R

R

0

0

4

-

ADC4

R

R

0

0

3

-

ADC3

R

R

0

0

2

-

ADC2

R

R

0

0

1

ADC9

ADC1

R

R

0

0

0

ADC8

ADC0

R

R

0

0

ADCH

ADCL

21.8.4.2

ADLAR = 1

Bit

Read/Write

Initial Value

7

ADC9

ADC1

R

R

0

0

6

ADC8

ADC0

R

R

0

0

5

ADC7

-

R

R

0

0

4

ADC6

-

R

R

0

0

3

ADC5

-

R

R

0

0

2

ADC4

-

R

R

0

0

1

ADC3

-

R

R

0

0

0

ADC2

-

R

R

0

0

ADCH

ADCL

21.8.5 Digital Input Disable Register 0 – DIDR0

4317K–AVR–03/2013

Bit

Read/Write

Initial Value

7

ADC7D

R/W

0

6

ADC6D

R/W

0

5

ADC5D

R/W

0

4

ADC4D

R/W

0

3

ADC3D

ACMPM

R/W

0

2

ADC2D

ACMP2D

R/W

0

1

ADC1D

R/W

0

0

ADC0D

R/W

0

DIDR0

251

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