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AT90PWM2B-16SU View Datasheet(PDF) - Atmel Corporation

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AT90PWM2B-16SU Datasheet PDF : 365 Pages
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AT90PWM2/3/2B/3B
The block diagram of the two amplifiers is shown on Figure 21-18.
Figure 21-18. Amplifiers block diagram
AMP0+
AMP0-
+
-
Sampling
Clock
Toward ADC MUX
(AMP0)
00
ADCK/8
01
ASY0
10
ASY1
01
ASY2
AMP0EN AMP0IS AMP0G1 AMP0G0 -
AMP0CSR
AMP1+
+
AMP1-
-
00
01
Sampling
10
Clock
01
- AMP0TS1AMP0TS0
Toward ADC MU
(AMP1)
ADCK/8
ASY0
ASY1
ASY2
AMP1EN AMP1IS AMP1G1 AMP1G0 -
AMP1CSR
- AMP1TS1AMP1TS0
21.10 Amplifier Control Registers
The configuration of the amplifiers are controlled via two dedicated registers AMP0CSR and
AMP1CSR. Then the start of conversion is done via the ADC control and status registers.
The conversion result is stored on ADCH and ADCL register which contain respectively the most
significant bits and the less significant bits.
21.10.1 Amplifier 0 Control and Status register – AMP0CSR
Bit
Read/Write
Initial Value
7
6
5
4
3
AMP0EN AMP0IS AMP0G1 AMP0G0
-
R/W
R/W
R/W
R/W
-
0
0
0
0
0
2
1
0
-
AMP0TS1 AMP0TS0 AMP0CSR
-
R/W
R/W
0
0
0
4317K–AVR–03/2013
256

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