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AT90PWM2B-16SU View Datasheet(PDF) - Atmel Corporation

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AT90PWM2B-16SU Datasheet PDF : 365 Pages
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AT90PWM2/3/2B/3B
26.6 SPI Timing Characteristics
See Figure 26-3 and Figure 26-4 for details.
Table 26-4. SPI Timing Parameters
Description
Mode
1
SCK period
Master
2
SCK high/low
Master
3
Rise/Fall time
Master
4
Setup
Master
5
Hold
Master
6
Out to SCK
Master
7
SCK to out
Master
8
SCK to out high
Master
9
SS low to out
Slave
10
SCK period
11
SCK high/low (1)
Slave
Slave
12
Rise/Fall time
Slave
13
Setup
Slave
14
Hold
Slave
15
SCK to out
Slave
16
SCK to SS high
Slave
17
SS high to tri-state
Slave
18
SS low to SCK
Slave
Min.
4 • tck
2 • tck
10
tck
20
2 • tck
Typ.
See Table 17-4
50% duty cycle
3.6
10
10
0.5 • tsck
10
10
15
15
10
Note:
In SPI Programming mode the minimum SCK high/low period is:
- 2 tCLCL for fCK < 12 MHz
- 3 tCLCL for fCK >12 MHz
Figure 26-3. SPI Interface Timing Requirements (Master Mode)
Max.
ns
1.6
SS
SCK
(CPOL = 0)
SCK
(CPOL = 1)
MISO
(Data Input)
MOSI
(Data Output)
6
45
MSB
...
7
MSB
...
1
2
2
LSB
LSB
3
8
4317K–AVR–03/2013
305

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