4317K–AVR–03/2013
AT90PWM2/3/2B/3B
Figure 26-7. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Timing Requirements(1)
XTAL1
BS1
OE
DATA
LOAD ADDRESS
(LOW BYTE)
tXLOL
tOLDV
ADDR0 (Low Byte)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
tBVDV
LOAD ADDRESS
(LOW BYTE)
DATA (Low Byte)
tOHDZ
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note: 1. ggThe timing requirements shown in Figure 26-5 (i.e., tDVXH, tXHXL, and tXLDX) also apply to
reading operation.
Table 26-7.
Symbol
VPP
IPP
tDVXH
tXLXH
tXHXL
tXLDX
tXLWL
tXLPH
tPLXH
tBVPH
tPHPL
tPLBX
tWLBX
tPLWL
tBVWL
tWLWH
tWLRL
tWLRH
tWLRH_CE
Parallel Programming Characteristics, VCC = 5V ± 10%
Parameter
Min. Typ.
Programming Enable Voltage
11.5
Programming Enable Current
Data and Control Valid before XTAL1 High
67
XTAL1 Low to XTAL1 High
200
XTAL1 Pulse Width High
150
Data and Control Hold after XTAL1 Low
67
XTAL1 Low to WR Low
0
XTAL1 Low to PAGEL high
0
PAGEL low to XTAL1 high
150
BS1 Valid before PAGEL High
67
PAGEL Pulse Width High
150
BS1 Hold after PAGEL Low
67
BS2/1 Hold after WR Low
67
PAGEL Low to WR Low
67
BS1 Valid to WR Low
67
WR Pulse Width Low
150
WR Low to RDY/BSY Low
0
WR Low to RDY/BSY High(1)
3.7
WR Low to RDY/BSY High for Chip Erase(2)
7.5
Max.
12.5
250
1
5
10
Units
V
A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
ms
ms
310