26.9 Parallel Programming Characteristics
AT90PWM2/3/2B/3B
Figure 26-5. Parallel Programming Timing, Including some General Timing Requirements
XTAL1
Data & Contol
(DATA, XA0/1, BS1, BS2)
PAGEL
WR
RDY/BSY
tDVXH
tXHXL
tXLWL
tXLDX
tBVPH
tPHPL
tPLBX t BVWL
tPLWL
tWLWH
WLRL
tWLBX
tWLRH
Figure 26-6. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
XTAL1
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
t XLXH
LOAD DATA LOAD DATA
(HIGH BYTE)
tXLPH
tPLXH
LOAD ADDRESS
(LOW BYTE)
BS1
PAGEL
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note: 1. The timing requirements shown in Figure 26-5 (i.e., tDVXH, tXHXL, and tXLDX) also apply to load-
ing operation.
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