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CSR8635 View Datasheet(PDF) - CSR plc

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Description
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CSR8635 Datasheet PDF : 105 Pages
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The RST# pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. CSR
recommends applying RST# for a period >5ms.
At reset the digital I/O pins are set to inputs for bidirectional pins and outputs are set to tristate.
10.10.1 Digital Pin States on Reset
Table 10.2 shows the pin states of CSR8635 QFN on reset.
Pin Name
I/O Type
Full Chip Reset Pin Name
I/O Type
Full Chip Reset
USB_DP
Digital bidirectional
N/A
PIO[9]
Digital bidirectional
PDS
USB_DN
Digital bidirectional
N/A
PIO[10]
Digital bidirectional
013 PIO[0]
27, 2 PIO[1]
ber PIO[2]
eptem PIO[3]
ay, S PIO[4]
- Frid PIO[5]
.cn PIO[6]
t.com PIO[7]
elpoin PIO[8]
Digital bidirectional
Digital bidirectional
Digital bidirectional
Digital bidirectional
Digital bidirectional
Digital bidirectional
Digital bidirectional
Digital bidirectional
Digital bidirectional
PUS
PUS
PDW
PDW
PDW
PDW
PDS
PDS
PUS
PIO[11]
PIO[12]
PIO[13]
PIO[14]
PIO[15]
PIO[16]
PIO[17]
PIO[18]
PIO[21]
Digital bidirectional
Digital bidirectional
Digital bidirectional
Digital bidirectional
Digital bidirectional
Digital bidirectional
Digital bidirectional
Digital bidirectional
Digital bidirectional
- exc Table 10.2: Pin States on Reset
.zhou Note:
en PUS = Strong pull-up
kev PDS = Strong pull-down
gbo PUW = Weak pull-up
r qin PDW = Weak pull-down
ed fo 10.10.2 Status After Reset
par The status of CSR8635 QFN after a reset is:
Pre â–  Warm reset: baud rate and RAM data remain available
â–  Cold reset: baud rate and RAM data not available
PDS
PDS
PUS
PDS
PUS
PUS
PUS
PDS
PDW
PDW
10.11 Automatic Reset Protection
CSR8635 QFN includes an automatic reset protection circuit which restarts/resets CSR8635 QFN when an unexpected
reset occurs, e.g. ESD strike or lowering of RST#. The automatic reset protection circuit enables resets from the VM
without the requirement for external circuitry.
Note:
The reset protection is cleared after typically 2s (1.6s min to 2.4s max).
If RST# is held low for >2.4s CSR8635 QFN turns off. A rising edge on VREGENABLE or VCHG is required to
power on CSR8635 QFN.
Production Information
© Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
Page 64 of 105
CS-303725-DSP5
www.csr.com

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