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CSR8635 View Datasheet(PDF) - CSR plc

Part Name
Description
Manufacturer
CSR8635 Datasheet PDF : 105 Pages
First Prev 61 62 63 64 65 66 67 68 69 70 Next Last
12 Example Application Schematic
VBAT VBUS
VBAT
3V3_USB
1V8_SMPS
1V35_SMPS
1V8_SMPS
Line Jack
Line Input / Microphone Auto Switch Circuit
S1
CON1
6
MFB
C2
C3
UNMATED
7
2u2
2u2
MATED
8
9
UNMATED
10
3 MATED
11
1 L 5
0 R
SHIELD
2
1
2 STX-3100-9N
tember 27, Mic1
L4
15nH
C17
15p
R2
2k2
C13 LINE_L
2u2
C14
2u2
C15 MIC_N
100n
C16 MIC_P
100n
JACK_DET_PIO
1V8
U1
LINE_BP
LINE_BN
C18
2u2
LINE/MIC_AN
LINE/MIC_AP
LINE/MIC_PIO
C19
2u2
Analogue 2xSPDT Switch
eg MAX4717 / TS3A24157 or alternatives
MIC_BIAS
C1
2u2
CHARGER
BYPASS REG
ep 50R
S i
, ANT
U2
2 OUT
IN 4
iday Bluetooth RF
3 GND GND 1
2.45GHz
50R
i
BT_RF
12 BT_RF
PCB Layout Notes CSR8635 QFnN- Fr Ensure the following components are placed next to CSR8635 QFN
.c and have good low impedance connections both to signal and GND
C2 and C3
om Ensure the following tracks have good low impedance connections
t.c (no via share and short thick tracks)
VSS_SMPS_1V8 to Battery Ground
in VSS_SMPS_1V35 to Battery Ground
o LX_1V8 to Inductor
lp LX_1V35 to Inductor
e L1 to C4 track
c L2 to C7 track
x C4 to VSS_SMPS_1V8
e C7 to VSS_SMPS_1V35
- VBAT to Battery and C2 - should be <1ohm from battery
u VCHG to charger connector and C1
o VDD_DIG to Ground
.zh Ensure good low impedance ground return path through GND plane for SMPSU
n current from C4 to VSS_SMPS_1V8 and C7 to VSS_SMPS_1V35 back to C3 & C4
e Ensure routing from L2 to pin 39 and from L2 to C8/9 & pins 11 & 13 are kept separate
ev CSR recommend low Rdc inductors (<0.5R) for L1 & L2 for optimum power efficiency
k For example Taiyo Yuden CB2012T4R7M
o Suggest analogue and digital grounds are separated if possible
ingb and star connected near VSS_AUDIO as shown
Ensure analogue tracks stay over Analogue ground as much as possible
SP100
STAR
L1
C4
C5
4u7 2u2
10n
C6
L2
C7
10n
4u7 4u7
C8
C9
15p
2u2
C10
470n
C11
100n
XTAL_IN 19
XT1
26MHz
VBAT
1V8 SMPS
1V35 SMPS
3V3
AUX LDO 1V35
ANA LDO 1V35
1V35
DIG LDO
XTAL_OUT 18
PIO[29] / LED[0]
PIO[30] / LED[1]
PIO[31] / LED[2]
37
36
66
PIO[0] / UART_RX
PIO[1] / UART_TX
PIO[6]
PIO[7]
PIO[8] / UART_RTS#
PIO[9] / UART_CTS#
PIO[18]
PIO[21]
59
60
62
57
61
58
65
64
LED_0
LED_1
LED_2
PIO_0
PIO_1
PIO_6
PIO_7
PIO_8
PIO_9
PIO_18
PIO_21
MIC BIAS
C12
2u2
PIO[2] / PCM1_IN / SPI_MOSI
PIO[3] / PCM1_OUT / SPI_MISO
PIO[4] / PCM1_SYNC / SPI_CS#
PIO[5] / PCM1_CLK / SPI_CLK
30
28
24
34
SPI_PCM# 29
PIO[12] / QSPI_FLASH_CS# / I2C_WP
PIO[10] / QSPI_FLASH_CLK / I2C_SCL
PIO[11] / QSPI_IO[0] / I2C_SDA
PIO[13] / QSPI_IO[1]
22
25
26
31
PIO[14] / UART_RX
PIO[15] / UART_TX
PIO[16] / UART_RTS#
PIO[17] / UART_CTS#
23
21
27
32
AIO[0] 20
USB_P
USB_N
56
55
RST# 35
PIO_2
PIO_3
PIO_4
PIO_5
SPI_PCM#
PIO_12
PIO_10
PIO_11
PIO_13
JACK_DET_PIO
LINE/MIC_PIO
PIO_16
PIO_17
AIO_0
USB_P
USB_N
RSTB
Left
Right
Speakers (16-32 Ohm)
LED outputs
PIO / UART
PIO / PCM1 / Debug SPI / I2S
SPI/PCM# high for SPI. Low for all other functions
PIO / Serial Flash / I2C
PIO / LINE-MIC Select / Jack Detect
Analogue Input / Output
USB (12Mbps)
Reset
Optional Ancilliary Circuits red for q Optional Fast charge
a 400mohm = 500mA
p VBUS
Pre CHG_EXT 1
VBAT_SENSE
Q100
BCX51
R104
1%
C105
4u7
R108
220mR
USB / Charger Interface
CON100
USB MINI-B
VBUS
D-
D+
ID
GND
1
2
3
4
5
VBUS
USB_N
USB_P
Lithium Polymer Battery
(battery protection built in)
VBAT
Li+ CELL
CON101
3.7V
Battery temperature sensor
1V35_SMPS R100
AIO_0
9k1
PIO_n
THERM
10k
D Q1
G
S
C102
10n
VBAT VBUS
D100
BAT54C
Typical LED's and Buttons
1V8
1V8
1V8
1V8
1V8
D101 D102 D103
R101
220R
R102
330R
R103
330R
S100
F4
S101
F3
S102
F2
S103 S104
VOL+ VOL-
Optional I2C EEPROM memory
1V8_SMPS C100
R105 R106 R107
2k2 2k2 2k2
PIO_12
PIO_10
PIO_11
U101
8
7
6
5
VCC
WP
SCL
SDA
10n
A0
A1
A2
VSS
1
2
3
4
24AAxxx
Optional 1x SPI FLASH memory
1V8_SMPS
C101
10n
PIO_11
PIO_13
1V8_SMPS
U100
8 VDD
5
2
3
7
SI/SIO0 CE
SO/SIO1 SCK
WP/SIO2
HOLD/SIO3
VSS
1
6
4
PIO_12
PIO_10
VBAT
400mR
SPI Flash
Size of EEPROM depends on voice prompt requirements
Connect VBAT_SENSE to VBAT
if not using this circuit
Figure 12.1: Single Microphone and Stereo Line Input
Production Information
© Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
Page 68 of 105
CS-303725-DSP5
www.csr.com

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