DSPIC33FJ16GS204-I/SP View Datasheet(PDF) - Microchip Technology
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Description
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DSPIC33FJ16GS204-I/SP Datasheet PDF : 346 Pages
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER (CONTINUED)
bit 3-2
bit 1
bit 0
CLDAT<1:0>: Data for PWMxH and PWMxL Pins if CLMODE is Enabled bits
FCLCONx<IFLTMOD> = 0: Normal Fault mode:
If current-limit active, then CLDAT<1> provides data for PWMxH.
If current-limit active, then CLDAT<0> provides data for PWMxL.
FCLCONx<IFLTMOD> = 1: Independent Fault mode:
CLDAT<1:0> is ignored.
SWAP<1:0>: SWAP PWMxH and PWMxL pins
1 = PWMxH output signal is connected to PWMxL pin and PWMxL signal is connected to PWMxH pins
0 = PWMxH and PWMxL pins are mapped to their respective pins
OSYNC: Output Override Synchronization bit
1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWM time base
0 = Output overrides via the OVDDAT<1:0> bits occur on next CPU clock boundary
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
© 2009 Microchip Technology Inc.
Preliminary
DS70318D-page 211
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