dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 15-18: LEBCONx: LEADING-EDGE BLANKING CONTROL REGISTER
R/W-0
PHR
bit 15
R/W-0
PHF
R/W-0
PLR
R/W-0
PLF
R/W-0
R/W-0
FLTLEBEN CLLEBEN
R/W-0
R/W-0
LEB<9:8>
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
LEB<7:3>
—
bit 7
U-0
U-0
—
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9-3
bit 2-0
PHR: PWMxH Rising Edge Trigger Enable bit
1 = Rising edge of PWMxH will trigger LEB counter
0 = LEB ignores rising edge of PWMxH
PHF: PWMH Falling Edge Trigger Enable bit
1 = Falling edge of PWMxH will trigger LEB counter
0 = LEB ignores falling edge of PWMxH
PLR: PWML Rising Edge Trigger Enable bit
1 = Rising edge of PWMxL will trigger LEB counter
0 = LEB ignores rising edge of PWMxL
PLF: PWML Falling Edge Trigger Enable bit
1 = Falling edge of PWMxL will trigger LEB counter
0 = LEB ignores falling edge of PWMxL
FLTLEBEN: Fault Input LEB Enable bit
1 = Leading-edge blanking is applied to selected Fault input
0 = Leading-edge blanking is not applied to selected Fault input
CLLEBEN: Current-Limit LEB Enable bit
1 = Leading-edge blanking is applied to selected current-limit input
0 = Leading-edge blanking is not applied to selected current-limit input
LEB: Leading-Edge Blanking for Current-Limit and Fault Inputs bits
Value is 8 nsec increments.
Unimplemented: Read as ‘0’
© 2009 Microchip Technology Inc.
Preliminary
DS70318D-page 215