DSPIC33FJ16GS102-I/SO View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
DSPIC33FJ16GS102-I/SO Datasheet PDF : 346 Pages
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
REGISTER 19-8: ADCPC3: A/D CONVERT PAIR CONTROL REGISTER 3(1)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
bit 15
R/W-0
IRQEN6
bit 7
R/W-0
PEND6
R/W-0
SWTRG6
R/W-0
R/W-0
R/W-0
R/W-0
TRGSRC6<4:0>
U-0
—
bit 8
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-8
bit 7
bit 6
bit 5
Unimplemented: Read as ‘0’
IRQEN6: Interrupt Request Enable 6 bit
1 = Enable IRQ generation when requested conversion of channels AN13 and AN12 is completed
0 = IRQ is not generated
PEND6: Pending Conversion Status 6 bit
1 = Conversion of channels AN13 and AN 12 is pending; set when selected trigger is asserted
0 = Conversion is complete
SWTRG6: Software Trigger 6 bit
1 = Start conversion of AN13 (INTREF) and AN12 (EXTREF) (if selected by TRGSRC bits)(2)
This bit is automatically cleared by hardware when the PEND6 bit is set.
0 = Conversion is not started
Note 1: This register is only implemented on the dsPIC33FJ16GS502 and dsPIC33FJ16GS504 devices.
2: If other conversions are in progress, conversion will be performed when the conversion resources are
available.
© 2009 Microchip Technology Inc.
Preliminary
DS70318D-page 257
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