DSPIC30F2012AT-20E/ML View Datasheet(PDF) - Microchip Technology
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Description
Manufacturer
DSPIC30F2012AT-20E/ML Datasheet PDF : 206 Pages
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dsPIC30F2011/2012/3012/3013
EXAMPLE 6-5: DATA EEPROM BLOCK WRITE
MOV
#LOW_ADDR_WORD,W0 ; Init pointer
MOV
#HIGH_ADDR_WORD,W1
MOV
W1,TBLPAG
MOV
#data1,W2
; Get 1st data
TBLWTL
MOV
W2,[ W0]++
#data2,W2
; write data
; Get 2nd data
TBLWTL
MOV
W2,[ W0]++
#data3,W2
; write data
; Get 3rd data
TBLWTL
MOV
W2,[ W0]++
#data4,W2
; write data
; Get 4th data
TBLWTL
MOV
W2,[ W0]++
#data5,W2
; write data
; Get 5th data
TBLWTL
MOV
W2,[ W0]++
#data6,W2
; write data
; Get 6th data
TBLWTL
MOV
W2,[ W0]++
#data7,W2
; write data
; Get 7th data
TBLWTL
MOV
W2,[ W0]++
#data8,W2
; write data
; Get 8th data
TBLWTL
MOV
W2,[ W0]++
#data9,W2
; write data
; Get 9th data
TBLWTL
MOV
W2,[ W0]++
#data10,W2
; write data
; Get 10th data
TBLWTL
MOV
W2,[ W0]++
#data11,W2
; write data
; Get 11th data
TBLWTL
MOV
W2,[ W0]++
#data12,W2
; write data
; Get 12th data
TBLWTL
MOV
W2,[ W0]++
#data13,W2
; write data
; Get 13th data
TBLWTL
MOV
W2,[ W0]++
#data14,W2
; write data
; Get 14th data
TBLWTL
MOV
W2,[ W0]++
#data15,W2
; write data
; Get 15th data
TBLWTL
MOV
W2,[ W0]++
#data16,W2
; write data
; Get 16th data
TBLWTL
MOV
W2,[ W0]++
#0x400A,W0
; write data. The NVMADR captures last table access address.
; Select data EEPROM for multi word op
MOV
DISI
W0,NVMCON
#5
; Operate Key to allow program operation
; Block all interrupts with priority <7 for
; next 5 instructions
MOV
#0x55,W0
MOV
W0,NVMKEY
MOV
#0xAA,W1
; Write the 0x55 key
MOV
BSET
W1,NVMKEY
NVMCON,#WR
; Write the 0xAA key
; Start write cycle
NOP
NOP
6.4 Write Verify
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
6.5 Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared;
also, the Power-up Timer prevents EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
DS70139F-page 58
© 2008 Microchip Technology Inc.
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