ST7PLITEU09M3TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST7PLITEU09M3TR Datasheet PDF : 115 Pages
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ST7LITEU05 ST7LITEU09
13.8.2 Output Driving Current
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Symbol
Parameter
Conditions
Min
Max Unit
VOL 1)
Output low level voltage for PA3/RESET standard
I/O pin (see Figure 57)
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 60)
IIO=+5mA,TA≤125°C
IIO=+2mA,TA≤125°C
IIO=+20mA,TA≤125°C
IIO=+8mA,TA≤125°C
1200
400
1300
750
VOH 2)
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 63)
IIO=-5mA,TA≤125°C
IIO=-2mA,TA≤125°C
VDD-1500
VDD-800
VOL 1)3)
Output low level voltage for PA3/RESET standard
I/O pin
(see Figure 56)
Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 59)
IIO=+2mA,TA≤125°C
IIO=+2mA,TA≤125°C
IIO=+8mA,TA≤125°C
500
180
mV
600
VOH 2)3)
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 62)
IIO=-2mA,TA≤125°C VDD-800
Output low level voltage for PA3/RESET standard
I/O pin (see Figure 55)
IIO=+2mA,TA≤125°C
700
VOL 1)3) Output low level voltage for a high sink I/O pin
IIO=+2mA,TA≤125°C
200
when 4 pins are sunk at same time
(see Figure 58)
IIO=+8mA,TA≤125°C
800
VOH 2)3)
Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 61)
IIO=-2mA,TA≤125°C VDD-900
Notes:
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
2. The IIO current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of
IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins do not have VOH.
3. Not tested in production, based on characterization results.
92/115
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