ST72324BLJ2B5 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72324BLJ2B5

3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface

STMicroelectronics 

ST72324Lxx

12.8 I/O PORT PIN CHARACTERISTICS

12.8.1 General Characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

VIL

VIH

Vhys

IINJ(PIN)3)

Input low level voltage 1)

Input high level voltage 1)

Schmitt trigger voltage hysteresis 2)

Injected Current on flash device pin

PB0

Injected Current on other I/O pins

0.7xVDD

0.8

0

ΣIINJ(PIN)3)

Total injected current (sum of all I/O

and control pins)

VDD=3V

Ilkg Input leakage current

VSS ≤ VIN ≤ VDD

IS

Static current consumption

Floating input mode4)

RPU Weak pull-up equivalent resistor 5) VIN=VSS

VDD=3V

110

180

CIO I/O pin capacitance

5

tf(IO)out Output high to low level fall time 1) CL=50pF

25

tr(IO)out Output low to high level rise time 1) Between 10% and 90%

25

tw(IT)in External interrupt pulse time 6)

1

Max

0.3xVDD

Unit

V

V

+4

±4

± 25

±1

200

250

mA

mA

µA

kΩ

pF

ns

tCPU

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be

respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD

while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the

corresponding VIN maximum must always be respected

4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for

example or an external pull-up or pull-down resistor (see Figure 65). Static peak current value taken at a fixed VIN value,

based on design simulation and technology characteristics, not tested in production. This value depends on VDD and tem-

perature values.

5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-

scribed in Figure 66).

6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

interrupt source.

Figure 65. Connecting Unused I/O Pins

VDD

10kΩ

ST72XXX

UNUSED I/O PORT

10kΩ

UNUSED I/O PORT

ST72XXX

Note: I/O can be left unconnected if it is configured as output

(0 or 1) by the software. This has the advantage of

greater EMC robustness and lower cost.

Figure 66. Typical IPU vs. VDD with VIN=VSS

90

80

Ta= 1 40°C

Ta= 9 5°C

70

Ta= 2 5°C

60

Ta=-45 °C

50

40

30

20

10

0

2 2 .5 3 3 .5 4 4 .5 5 5 .5 6

V dd (V )

124/154

1

Share Link: