ST72324BLJ2B5 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72324BLJ2B5

3V range 8-bit MCU with 8 to 32K Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI interface

STMicroelectronics 

ST72324Lxx

12.9 CONTROL PIN CHARACTERISTICS

12.9.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage 1)

Flash versions

ROM versions

VIH Input high level voltage 1)

Flash versions

ROM versions

Vhys Schmitt trigger voltage hysteresis 2)

VOL Output low level voltage1)

IIO=+2mA

IIO

Output current on RESET pin when

driven low internally

0.85xVDD

0.7xVDD

2.5

0.3

2

0.16xVDD

0.3xVDD

V

0.7

V

mA

RON Weak pull-up equivalent resistor

tw(RSTL)out Generated reset pulse duration

th(RSTL)in External reset pulse hold time 4)

tg(RSTL)in Filtered glitch duration 5)

VDD=3V

50

Internal reset sources

13

2.5

82

150

kΩ

30

721)

µs

µs

200

ns

Figure 73. Typical Application with RESET pin 6)7)8)

Recommended

VDD

VDD

VDD

ST72XXX

USER

EXTERNAL

RESET

CIRCUIT 5)

Required

0.01µF

4.7kΩ

0.01µF

RON

Filter

INTERNAL

RESET

PULSE

GENERATOR

WATCHDOG RESET

Notes:

1. Data guaranteed by design, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels.

3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS.

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on

the RESET pin with a duration below th(RSTL)in can be ignored.

5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-

vironments.

6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device

can be damaged when the ST7 generates an internal reset (watchdog).

7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below

the VIL max. level specified in Section 12.9.1 . Otherwise the reset will not be taken into account internally.

8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure

that the current source on the RESET pin (by an external pull-up for example) is less than the absolute maximum value

specified for IINJ(RESET) in Section 12.2.2 on page 111.

127/154

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