Electrical characteristics
STM8S005K6 STM8S005C6
Figure 9: fCPUmax versus VDD
f
CPU
(MHz)
Functionality
not
16
guaranteed
in this area 12
8
4
0
Functionality guaranteed
@TA-40 to 85 °C
2.95
4.0
5.0
5.5
Supply voltage
Symbol
tVDD
tTEMP
Table 18: Operating conditions at power-up/power-down
Parameter
Conditions
Min Typ
Max Unit
VDD rise time rate
2.0 (1)
∞
µs/V
VDD fall time rate
2.0 (1)
∞
Reset releasedelay VDD rising
1.7 (1) ms
VIT+
Power-on reset
threshold
2.65 2.8
2.95 V
VIT-
Brown-out reset
threshold
2.58 2.7
2.88
VHYS(BOR) Brown-out reset
hysteresis
70
mV
(1) Guaranteed by design, not tested in production.
9.3.1
VCAP external capacitor
Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the
VCAP pin. CEXT is specified in the Operating conditions section. Care should be taken to limit
the series inductance to less than 15 nH.
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