ST7PLIT115BF1M3 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST7PLIT115BF1M3

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI

STMicroelectronics 

ST7LITE1xB

16 REVISION HISTORY

Date

20-Dec-05

20-July-06

15-Sept-06

Revision

Main changes

1 Initial release on internet

Added reset default state in bold for RESET, PC0 and PC1 in Table 1, “Device Pin Descrip-

tion,” on page 7

Changed note below Figure 9 on page 17 and the last paragraph of “ACCESS ERROR HAN-

DLING” on page 18

Modified note 3 in Table 2, “Hardware Register Map,” on page 10, changed LTICR reset val-

ue and replaced h by b for LTCSR1, ATCSR and SICSR reset values

Added note to Figure 14 on page 26

Modified caution in section 7.2 on page 23

Added note 2 in “EXTERNAL INTERRUPT CONTROL REGISTER (EICR)” on page 38 and

changed “External Interrupt Function” on page 48

Removed references to true open drain in Table 8 on page 50, Table 9 on page 51 and notes

Replaced Auto reload timer 3 by Auto reload timer 4 in section 11.2 on page 57

Modified the BA bit description in the BREAKCR register in section 11.2.6 on page 70

Changed order of Section 11.3.3.2 and section 11.3.3.3 on page 80 and removed two para-

graphs before section 11.3.4 on page 81

Modified Section 11.3.3.2

Modified bit names in the description of LTARR and LTCNTR registers in section 11.3.6 on

page 81

Added important note in section 11.6.3 on page 100 and added note to CHYST bit descrip-

tion in section 11.6.4 on page 102

Modified CINV bit description in section 11.6.4 on page 102 and Figure 62 on page 101

Changed LTCSR2 reset values in Table 2 on page 10 and in section 11.3.6 on page 81

Modified section 13.2.2 on page 111 (IIO values)

Modified Section 13.3.1 and section 13.3.2 on page 112

Removed VtPOR min value in section 13.3.3.1 on page 113

2 Modified section 13.3.4 on page 114

Modified section 13.3.5 on page 114

Modified section 13.3.5.1 on page 115 and section 13.3.5.2 on page 117

Modified temperature range in section 13.3.5.3 on page 119

Modified section 13.4.1 on page 121

Added note in section 13.5.3 on page 124

Removed figures “PLLx4 and PLLx8 Output vs CLKIN frequency”

Updated section 13.5.4 on page 125

Modified section 13.6 on page 126

Modified Section 13.7.1 and section 13.7.2 on page 127

Modified section 13.10.1 on page 137 (tsu(SS), tv(MO) and th(MO))

Modified Figure 108 (CPHA=1) and Figure 109 on page 138 (tv(MO) , th(MO))

Removed empty figure “Typical IPU vs. VDD with VIN=VSS” in section 13.8.1 on page 129 and

modified note 3

Modified temperature range in section 13.8.2 on page 130

Modified section 13.9.1 on page 135

Added “related Application notes” in section 13.11 on page 139

Removed EMC protection circuitry in Figure 106 on page 136 (device works correctly without

these components)

Modified ADC accuracy table in section 13.11 on page 139

Modified temperature range in Section 13.12, Section 13.13 and section 13.14 on page 143

Modified Table 27 on page 150

Added note 3 to ED and EL in Table “ADC Accuracy with VDD=5.0V” on page 140

Modified section 14.2 on page 148

Modified section 15.2 on page 151 (part numbers in QFN20 package)

Updated section 15.3 on page 153

Removed QFN20 pinout and mechanical data.

3

Modified description of CNTR[11:0] bits in section 11.2.6 on page 72

Added “External Clock Source” on page 124 and Figure 78 on page 124

Modified Table 1.

157/159

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