ST7PLIT110BF0M3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST7PLIT110BF0M3
STMicroelectronics
ST7PLIT110BF0M3 Datasheet PDF : 159 Pages
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ST7LITE1xB
I/O PORTS (Cont’d)
10.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION
The I/O port register configurations are summa-
rised as follows.
Standard Ports
PA7:0, PB6:0
MODE
floating input
pull-up input
open drain output
push-pull output
DDR OR
0
0
0
1
1
0
1
1
Interrupt Ports
Ports where the external interrupt capability is
selected using the EISR register
MODE
floating input
pull-up interrupt input
open drain output
push-pull output
DDR OR
0
0
0
1
1
0
1
1
PC1:0 (multiplexed with OSC1,OSC2)
MODE
floating input
push-pull output
DDR
0
1
The selection between OSC1 or PC0 and OSC2 or
PC1 is done by option byte. Refer to section 15.1
on page 149. Interrupt capability is not available
on PC1:0.
Note: PCOR not implemented but p-transistor al-
ways active in output mode (refer to Figure 32 on
page 50)
Table 10. Port Configuration (Standard ports)
Port
Port A
Port B
Pin name
PA7:0
PB6:0
OR = 0
floating
floating
Input
OR = 1
pull-up
pull-up
Output
OR = 0
open drain
open drain
OR = 1
push-pull
push-pull
Note: On ports where the external interrupt capability is selected using the EISR register, the configura-
tion will be as follows:
Port
Port A
Port B
Pin name
PA7:0
PB6:0
OR = 0
floating
floating
Input
OR = 1
pull-up interrupt
pull-up interrupt
Output
OR = 0
open drain
open drain
OR = 1
push-pull
push-pull
Table 11. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
PADR
MSB
LSB
0000h
Reset Value
1
1
1
1
1
1
1
1
PADDR
MSB
LSB
0001h
Reset Value
0
0
0
0
0
0
0
0
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