ST7262xxx
Table 2. Hardware Register Map
Address
Block
Register
Label
Register Name
Reset
Status
Remarks
0000h
0001h
Port A
PADR
PADDR
Port A Data Register
Port A Data Direction Register
00h1)
00h
R/W2)
R/W2)
0002h
0003h
Port B
PBDR
PBDDR
Port B Data Register
Port B Data Direction Register
00h1)
00h
R/W2)
R/W2)
0004h
0005h
) 0006h
t(s 0007h
c 0008h
du 0009h
ro 000Ah
P 000Bh
te 000Ch
le 000Dh
so 000Eh
b 0010h
O 0011h
- 0012h
) 0013h
t(s 0014h
uc 0015h
d 0016h
ro 0017h
0018h
P 0019h
te 001Ah
001Bh
le 001Ch
so 001Dh
b 001Eh
O001Fh
Port C
Port D
ADC
WDG
PCDR
PCDDR
Port C Data Register
Port C Data Direction Register
PDDR
PDDDR
Port D Data Register
Port D Data Direction Register
ITRFRE1 Interrupt Register 1
MISC
Miscellaneous Register
ADCDRMSB ADC Data Register (bit 9:2)
ADCDRLSB ADC Data Register (bit 1:0)
ADCCSR ADC Control Status Register
WDGCR
Watchdog Control Register
Reserved Area (3 Bytes)
SPI
PWM ART
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control Status Register
PWMDCR1
PWMDCR0
PWMCR
ARTCSR
ARTCAR
ARTARR
ARTICCSR
ARTICR1
ARTICR2
PWM AR Timer Duty Cycle Register 1
PWM AR Timer Duty Cycle Register 0
PWM AR Timer Control Register
Auto-Reload Timer Control/Status Register
Auto-Reload Timer Counter Access Register
Auto-Reload Timer Auto-Reload Register
ART Input Capture Control/Status Register
ART Input Capture Register 1
ART Input Capture Register 2
SCIERPR
SCIETPR
SCI Extended Receive Prescaler register
SCI Extended Transmit Prescaler Register
Reserved Area
00h1)
00h
00h1)
00h
00h
00h
00h
00h
00h
7Fh
xxh
0xh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
--
R/W2)
R/W2)
R/W2)
R/W2)
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
0020h
0021h
SCI
SCISR
SCIDR
SCI Status register
SCI Data register
C0h Read Only
xxh
R/W
0022h
SCIBRR
SCI Baud Rate Register
00h R/W
0023h
SCICR1
SCI Control Register 1
x000 0000b R/W
0024h
SCICR2
SCI Control Register 2
00h R/W
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Doc ID 6996 Rev 5