ST72P623 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72P623

LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS, FLASH OR ROM MEMORY, LVD, WDG, 10-BIT ADC, 2 TIMERS, SCI, SPI

STMicroelectronics 

ST7262xxx

Figure 14. Clock block diagram

x2

Slow

Mode

%

1/2/4/8

fCPU 8/4/2/1 MHz

(or 4/2/1/0.5 MHz)

to CPU and

peripherals

SMS[1:0]

%3

) OSC12/6

uct(s 12 or

d 6 MHz

ro Crystal

0

%2

1

MCO pin

6 MHz (USB)

lete P 6.2 RESET

o The Reset procedure is used to provide an orderly

s software start-up or to exit low power modes.

Ob Three reset modes are provided: a low voltage re-

- set, a watchdog reset and an external reset at the

) RESET pin.

t(s A reset causes the reset vector to be fetched from

addresses FFFEh and FFFFh in order to be loaded

c into the PC and with program execution starting

du from this point.

ro An internal circuitry provides a 514 CPU clock cy-

cle delay from the time that the oscillator becomes

P active.

te Caution: When the ST7 is unprogrammed or fully

le erased, the Flash is blank and the RESET vector

o is not programmed. For this reason, it is recom-

s mended to keep the RESET pin in low state until

b programming mode is entered, in order to avoid

O unwanted behaviour.

It is recommended to make sure that the VDD supply

voltage rises monotonously when the device is ex-

iting from Reset, to ensure the application functions

properly.

6.2.2 Watchdog Reset

When a watchdog reset occurs, the RESET pin is

pulled low permitting the MCU to reset other devic-

es as when low voltage reset (Figure 15).

6.2.3 External Reset

The external reset is an active low input signal ap-

plied to the RESET pin of the MCU.

As shown in Figure 18, the RESET signal must

stay low for a minimum of one and a half CPU

clock cycles.

An internal Schmitt trigger at the RESET pin is pro-

vided to improve noise immunity.

6.2.1 Low Voltage Reset

Figure 15. Low Voltage Reset functional Diagram

Low voltage reset circuitry generates a reset when

VDD is:

■ below VIT+ when VDD is rising,

■ below VIT- when VDD is falling.

During low voltage reset, the RESET pin is held low,

thus permitting the MCU to reset other devices.

Notes:

The Low Voltage Detector can be disabled by set-

ting the LVD bit of the Option byte.

VDD

LOW VOLTAGE

RESET

FROM

WATCHDOG

RESET

RESET

INTERNAL

RESET

Doc ID 6996 Rev 5

21/139

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