ST72P623 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72P623

LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS, FLASH OR ROM MEMORY, LVD, WDG, 10-BIT ADC, 2 TIMERS, SCI, SPI

STMicroelectronics 

ST7262xxx

POWER SAVING MODES (Cont’d)

Figure 25. HALT Mode Flow Chart

8.3 HALT MODE

HALT INSTRUCTION

The HALT mode is the MCU lowest power con-

sumption mode. The HALT mode is entered by ex-

ecuting the HALT instruction. The internal oscilla-

tor is then turned off, causing all internal process-

ing to be stopped, including the operation of the

on-chip peripherals.

OSCILLATOR

PERIPH. CLOCK

CPU CLOCK

OFF

OFF

OFF

When entering HALT mode, the I bit in the Condi-

I-BIT

CLEARED

tion Code Register is cleared. Thus, any of the ex-

ternal interrupts (ITi or USB end suspend mode),

) are allowed and if an interrupt occurs, the CPU

t(s clock becomes active.

The MCU can exit HALT mode on reception of ei-

uc ther an external interrupt on ITi, an end suspend

d mode interrupt coming from USB peripheral, or a

ro reset. The oscillator is then turned on and a stabi-

lization time is provided before releasing CPU op-

P eration. The stabilization time is 514 CPU clock cy-

te cles.

After the start up delay, the CPU continues opera-

le tion by servicing the interrupt which wakes it up or

Obsolete Product(s) - Obso by fetching the reset vector if a reset wakes it up.

N

N

EXTERNAL

INTERRUPT*

RESET

Y

Y

OSCILLATOR

PERIPH. CLOCK

CPU CLOCK

I-BIT

ON

ON

ON

SET

514 CPU CLOCK

CYCLES DELAY

FETCH RESET VECTOR

OR SERVICE INTERRUPT

Note: Before servicing an interrupt, the CC register is

pushed on the stack. The I-Bit is set during the inter-

rupt routine and cleared when the CC register is

popped.

Doc ID 6996 Rev 5

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