ST72P623 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72P623

LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS, FLASH OR ROM MEMORY, LVD, WDG, 10-BIT ADC, 2 TIMERS, SCI, SPI

STMicroelectronics 

ST7262xxx

10 ON-CHIP PERIPHERALS

10.1 WATCHDOG TIMER (WDG)

10.1.1 Introduction

If the watchdog is activated (the WDGA bit is set)

The Watchdog timer is used to detect the occur-

rence of a software fault, usually generated by ex-

ternal interference or by unforeseen logical condi-

and when the 7-bit timer (bits T[6:0]) rolls over

from 40h to 3Fh (T6 becomes cleared), it initiates

a reset cycle by driving low the reset pin for 30µs.

tions, which causes the application program to The application program must write in the CR reg-

abandon its normal sequence. The Watchdog cir- ister at regular intervals during normal operation to

cuit generates an MCU reset on expiry of a pro- prevent an MCU reset. This downcounter is free-

grammed time period, unless the program refresh-

es the counter’s contents before the T6 bit be-

) comes cleared.

t(s 10.1.2 Main Features

c ■ Programmable free-running downcounter (64

u increments of 65536 CPU cycles)

d ■ Programmable reset

ro ■ Reset (if watchdog activated) when the T6 bit

P reaches zero

te ■ Hardware Watchdog selectable by option byte

ole 10.1.3 Functional Description

bs The counter value stored in the CR register (bits

O T[6:0]), is decremented every 65,536 machine cy-

- cles, and the length of the timeout period can be

) programmed by the user in 64 increments.

t(s Figure 30. Watchdog Block Diagram

uc RESET

running: it counts down even if the watchdog is di-

abled The value to be stored in the CR register

must be between FFh and C0h (see Table 14):

– The WDGA bit is set (watchdog enabled)

– The T6 bit is set to prevent generating an imme-

diate reset

– The T[5:0] bits contain the number of increments

which represents the time delay before the

watchdog produces a reset.

Table 14.Watchdog Timing (fCPU = 8 MHz)

CR Register

initial value

WDG timeout period

(ms)

Max

FFh

524.288

Min

C0h

8.192

Obsolete Prod WDGA T6

WATCHDOG CONTROL REGISTER (CR)

T5 T4 T3 T2 T1 T0

7-BIT DOWNCOUNTER

fCPU

CLOCK DIVIDER

÷65536

Doc ID 6996 Rev 5

41/139

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