ST72P623 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72P623

LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS, FLASH OR ROM MEMORY, LVD, WDG, 10-BIT ADC, 2 TIMERS, SCI, SPI

STMicroelectronics 

ST7262xxx

PWM AUTO-RELOAD TIMER (Cont’d)

Input capture function

This mode allows the measurement of external

signal pulse widths through ICRx registers.

During HALT mode, input capture is inhibited (the

ICRx is never re-loaded) and only the external in-

terrupt capability can be used.

Each input capture can generate an interrupt inde-

pendently on a selected input signal transition.

This event is flagged by a set of the corresponding External interrupt capability

CFx bits of the Input Capture Control/Status regis-

ter (ICCSR).

This mode allows the Input capture capabilities to

be used as external interrupt sources.

These input capture interrupts are enabled

through the CIEx bits of the ICCSR register.

The active transition (falling or rising edge) is soft-

t(s) ware programmable through the CSx bits of the

ICCSR register.

c The read only input capture registers (ICRx) are

u used to latch the auto-reload counter value when a

rod transition is detected on the ARTICx pin (CFx bit

set in ICCSR register). After fetching the interrupt

P vector, the CFx flags can be read to identify the in-

te terrupt source.

le Note: After a capture detection, data transfer in

the ICRx register is inhibited until the ARTICCSR

so register is read (clearing the CFx bit).

b The timer interrupt remains pending while the CFx

flag is set when the interrupt is enabled (CIEx bit

O set). This means, the ARTICCSR register has to

- be read at each capture event to clear the CFx

t(s) flag.

uc The timing resolution is given by auto-reload coun-

d ter cycle time (1/fCOUNTER).

The edge sensitivity of the external interrupts is

programmable (CSx bit of ICCSR register) and

they are independently enabled through CIEx bits

of the ICCSR register. After fetching the interrupt

vector, the CFx flags can be read to identify the in-

terrupt source.

The interrupts are synchronized on the counter

clock rising edge (Figure 36).

During HALT mode, the external interrupts can still

be used to wake up the micro (if CIEx bit is set).

Figure 36. ART External Interrupt

fCOUNTER

ARTICx PIN

CFx FLAG

INTERRUPT

t

Pro Figure 37. Input Capture Timing Diagram

lete fCOUNTER

ObsoCOUNTER

01h

02h

03h

04h

05h

06h

07h

ARTICx PIN

INTERRUPT

CFx FLAG

xxh

ICRx REGISTER

04h

t

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Doc ID 6996 Rev 5

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