ST72P623 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72P623

LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS, FLASH OR ROM MEMORY, LVD, WDG, 10-BIT ADC, 2 TIMERS, SCI, SPI

STMicroelectronics 

ST7262xxx

INTERRUPTS (Cont’d)

INTERRUPT REGISTER 1 (ITRFRE1)

Bit 5:4 = CTL[1:0] IT[10:9]1nterrupt Sensitivity

Address: 0008h - Read/Write

Reset Value: 0000 0000 (00h)

7

These bits are set and cleared by software. They

are used to configure the edge and level sensitivity

of the IT10 and IT9 external interrupt pins (this

means that both must have the same sensitivity).

0

CTL1 CTL0 IT[10:9] Sensitivity

IT8E IT7E IT6E IT5E IT4E IT3E IT2E IT1E

0

0

Falling edge and low level

0

1

Rising edge only

1

0

Falling edge only

Bit 7:0 = ITiE Interrupt Enable

0: I/O pin free for general purpose I/O

) 1: ITi external interrupt enabled.

t(s Note: The corresponding interrupt is generated

c when:

u – a rising edge occurs on the IT5/IT6 pins

rod – a falling edge occurs on the IT1, 2, 3, 4, 7 and 8

pins

1

1

Rising and falling edge

Bit 3:0 = ITiE Interrupt Enable

0: I/O pin free for general purpose I/O

1: ITi external interrupt enabled.

te P INTERRUPT REGISTER 2 (ITRFRE2)

le Address: 0039h - Read/Write

so Reset Value: 0000 0000 (00h)

Ob 7

0

) - CTL3 CTL2 CTL1 CTL0 IT12E IT11E IT10E IT9E

uct(s Bit 7:6 = CTL[3:2] IT[12:11] Interrupt Sensitivity

d These bits are set and cleared by software. They

ro are used to configure the edge and level sensitivity

P of the IT12 and IT11 external interrupt pins (this

means that both must have the same sensitivity).

lete CTL3

o 0

s 0

Ob 1

CTL2

0

1

0

IT[12:11] Sensitivity

Falling edge and low level

Rising edge only

Falling edge only

1

1

Rising and falling edge

28/139

Doc ID 6996 Rev 5

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