ST7262xxx
Address
Block
Register
Label
Register Name
Reset
Status
Remarks
0025h
USBPIDR USB PID Register
x0h Read Only
0026h
USBDMAR USB DMA Address register
xxh
R/W
0027h
USBIDR
USB Interrupt/DMA Register
x0h R/W
0028h
USBISTR USB Interrupt Status Register
00h R/W
0029h
USBIMR
USB Interrupt Mask Register
00h R/W
002Ah
USBCTLR USB Control Register
06h R/W
002Bh
USB
USBDADDR USB Device Address Register
00h R/W
002Ch
USBEP0RA USB Endpoint 0 Register A
0000 xxxxb R/W
002Dh
002Eh
) 002Fh
t(s 0030h
0031h
uc 0032h
d to
ro 0035h
P 0036h
te 0037h
le 0038h
so 0039h
Ob 003Ah
- to
) 003Fh
USBEP0RB
USBEP1RA
USBEP1RB
USBEP2RA
USBEP2RB
USB Endpoint 0 Register B
USB Endpoint 1 Register A
USB Endpoint 1 Register B
USB Endpoint 2 Register A
USB Endpoint 2 Register B
Reserved Area (4 Bytes)
TBU
FLASH
TBUCV
TBUCSR
FCSR
ITRFRE2
TBU Counter Value Register
TBU Control/Status Register
Flash Control/Status Register
Interrupt Register 2
Reserved Area (6 Bytes)
80h R/W
0000 xxxxb R/W
0000 xxxxb R/W
0000 xxxxb R/W
0000 xxxxb R/W
00h R/W
00h R/W
00h R/W
00h R/W
t(s Legend: x=undefined, R/W=read/write
uc Notes:
d 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-
ro tion, the values of the I/O pins are returned instead of the DR register contents.
Obsolete P 2. The bits associated with unavailable pins must always be kept at their reset value.
Doc ID 6996 Rev 5
13/139