S25FL256SDPMFVC03 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL256SDPMFVC03
Cypress Semiconductor
S25FL256SDPMFVC03 Datasheet PDF : 144 Pages
| |||
S25FL128S, S25FL256S
Although host software in some cases is used to directly control the SPI interface signals, the hardware interfaces of the host
system and the memory device generally handle the details of signal relationships and timing. For this reason, signal
relationships and timing are not covered in detail within this software interface focused section of the document. Instead, the
focus is on the logical sequence of bits transferred in each command rather than the signal timing and relationships. Following
are some general signal relationship descriptions to keep in mind. For additional information on the bit level format and signal
timing relationships of commands, see Command Protocol on page 15.
– The host always controls the Chip Select (CS#), Serial Clock (SCK), and Serial Input (SI) - SI for single bit wide transfers. The
memory drives Serial Output (SO) for single bit read transfers. The host and memory alternately drive the IO0-IO3 signals
during Dual and Quad transfers.
– All commands begin with the host selecting the memory by driving CS# low before the first rising edge of SCK. CS# is kept
low throughout a command and when CS# is returned high the command ends. Generally, CS# remains low for 8-bit transfer
multiples to transfer byte granularity information. Some commands will not be accepted if CS# is returned high not at an 8-bit
boundary.
9.1 Command Set Summary
9.1.1
Extended Addressing
To accommodate addressing above 128 Mb, there are three options:
1. New instructions are provided with 4-byte address, used to access up to 32 Gb of memory.
Instruction Name
4FAST_READ
4READ
4DOR
4QOR
4DIOR
4QIOR
4DDRFR
4DDRDIOR
4DDRQIOR
4PP
4QPP
4P4E
4SE
Description
Read Fast (4-byte Address)
Read (4-byte Address)
Read Dual Out (4-byte Address)
Read Quad Out (4-byte Address)
Dual I/O Read (4-byte Address)
Quad I/O Read (4-byte Address)
Read DDR Fast (4-byte Address)
DDR Dual I/O Read (4-byte Address)
DDR Quad I/O Read (4-byte Address)
Page Program (4-byte Address)
Quad Page Program (4-byte Address)
Parameter 4-kB Erase (4-byte Address)
Erase 64/256 kB (4-byte Address)
Code (Hex)
0C
13
3C
6C
BC
EC
0E
BE
EE
12
34
21
DC
Document Number: 001-98283 Rev. *I
Page 64 of 144
Share Link: 