S25FL256SDPMFVC03 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL256SDPMFVC03

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

Table 7.10 Latency Codes for SDR High Performance

Freq.

(MHz)

LC

≤ 50 11

≤ 80 00

≤ 90 01

≤104 10

≤133 10

Read

(03h, 13h)

Mode

0

Dummy

0

-

-

-

-

-

-

-

-

Fast Read

(0Bh, 0Ch)

Mode

0

Dummy

0

0

8

0

8

0

8

0

8

Read Dual Out

(3Bh, 3Ch)

Mode

0

Dummy

0

0

8

0

8

0

8

-

-

Read Quad Out

(6Bh, 6Ch)

Mode

0

Dummy

0

0

8

0

8

0

8

-

-

Dual I/O Read

(BBh, BCh)

Mode

0

Dummy

4

0

4

0

5

0

6

-

-

Quad I/O Read

(EBh, ECh)

Mode

2

Dummy

1

2

4

2

4

2

5

-

-

Table 7.11 Latency Codes for DDR High Performance

Freq. (MHz) LC

≤ 50

11

≤ 66

00

≤ 66

01

≤ 66

10

DDR Fast Read

(0Dh, 0Eh)

Mode

Dummy

0

4

0

5

0

6

0

7

DDR Dual I/O Read

(BDh, BEh)

Mode

Dummy

0

4

0

6

0

7

0

8

Read DDR Quad I/O

(EDh, EEh)

Mode

Dummy

1

3

1

6

1

7

1

8

Table 7.12 Latency Codes for SDR Enhanced High Performance

Freq.

(MHz)

LC

≤ 50 11

≤ 80 00

≤ 90 01

≤104 10

≤133 10

Read

(03h, 13h)

Mode

0

Dummy

0

-

-

-

-

-

-

-

-

Fast Read

(0Bh, 0Ch)

Mode

0

Dummy

0

0

8

0

8

0

8

0

8

Read Dual Out

(3Bh, 3Ch)

Mode

0

Dummy

0

0

8

0

8

0

8

-

-

Read Quad Out

(6Bh, 6Ch)

Mode

0

Dummy

0

0

8

0

8

0

8

-

-

Dual I/O Read

(BBh, BCh)

Mode

4

Dummy

0

4

0

4

1

4

2

-

-

Quad I/O Read

(EBh, ECh)

Mode

2

Dummy

1

2

4

2

4

2

5

-

-

Table 7.13 Latency Codes for DDR Enhanced High Performance

Freq. (MHz) LC

≤ 50

11

≤ 66

00

≤ 66

01

≤ 66

10

≤ 80

00

≤ 80

01

≤ 80

10

DDR Fast Read

(0Dh, 0Eh)

Mode

4

Dummy

1

4

2

4

4

4

5

4

2

4

4

4

5

DDR Dual I/O Read

(BDh, BEh)

Mode

2

Dummy

2

2

4

2

5

2

6

2

4

2

5

2

6

Read DDR Quad I/O

(EDh, EEh)

Mode

1

Dummy

3

1

6

1

7

1

8

1

6

1

7

1

8

Note:

1. When using DDR I/O commands with the Data Learning Pattern (DLP) enabled, a Latency Code that provides 5 or more dummy cycles should be selected to allow 1

cycle of additional time for the host to stop driving before the memory starts driving the 4 cycle DLP. It is recommended to use LC 10 for DDR Fast Read, LC 01 for

DDR Dual IO Read, and LC 00 for DDR Quad IO Read, if the Data Learning Pattern (DLP) for DDR is used.

Document Number: 001-98283 Rev. *I

Page 51 of 144

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