S25FL256SDPMFVC03 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL256SDPMFVC03

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

8. Data Protection

8.1 Secure Silicon Region (OTP)

The device has a 1024-byte One Time Program (OTP) address space that is separate from the main flash array. The OTP area is

divided into 32, individually lockable, 32-byte aligned and length regions.

The OTP memory space is intended for increased system security. OTP values can “mate” a flash component with the system CPU/

ASIC to prevent device substitution. See OTP Address Space on page 47, One Time Program Array Commands on page 109, and

OTP Read (OTPR 4Bh) on page 109.

8.1.1

Reading OTP Memory Space

The OTP Read command uses the same protocol as Fast Read. OTP Read operations outside the valid 1-kB OTP address range

will yield indeterminate data.

8.1.2

Programming OTP Memory Space

The protocol of the OTP programming command is the same as Page Program. The OTP Program command can be issued multiple

times to any given OTP address, but this address space can never be erased. The valid address range for OTP Program is depicted

in Figure 7.1, OTP Address Space on page 47. OTP Program operations outside the valid OTP address range will be ignored and

the WEL in SR1 will remain high (set to 1). OTP Program operations while FREEZE = 1 will fail with P_ERR in SR1 set to 1.

8.1.3

Cypress Programmed Random Number

Cypress standard practice is to program the low order 16 bytes of the OTP memory space (locations 0x0 to 0xF) with a 128-bit

random number using the Linear Congruential Random Number Method. The seed value for the algorithm is a random number

concatenated with the day and time of tester insertion.

8.1.4

Lock Bytes

The LSB of each Lock byte protects the lowest address region related to the byte, the MSB protects the highest address region

related to the byte. The next higher address byte similarly protects the next higher 8 regions. The LSB bit of the lowest address Lock

Byte protects the higher address 16 bytes of the lowest address region. In other words, the LSB of location 0x10 protects all the Lock

Bytes and RFU bytes in the lowest address region from further programming. See Section 7.4, OTP Address Space on page 47.

8.2 Write Enable Command

The Write Enable (WREN) command must be written prior to any command that modifies non-volatile data. The WREN command

sets the Write Enable Latch (WEL) bit. The WEL bit is cleared to 0 (disables writes) during power-up, hardware reset, or after the

device completes the following commands:

– Reset

– Page Program (PP)

– Sector Erase (SE)

– Bulk Erase (BE)

– Write Disable (WRDI)

– Write Registers (WRR)

– Quad-input Page Programming (QPP)

– OTP Byte Programming (OTPP)

Document Number: 001-98283 Rev. *I

Page 57 of 144

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