S25FL256SDPMFVC03 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL256SDPMFVC03

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

Top or Bottom Protection (TBPROT) CR1[5]: This bit defines the operation of the Block Protection bits BP2, BP1, and BP0 in the

Status Register. As described in the status register section, the BP2-0 bits allow the user to optionally protect a portion of the array,

ranging from 1/64, 1/4, 1/2, etc., up to the entire array. When TBPROT is set to a 0 the Block Protection is defined to start from the

top (maximum address) of the array. When TBPROT is set to a 1 the Block Protection is defined to start from the bottom (zero

address) of the array. The TBPROT bit is OTP and set to a 0 when shipped from Cypress. If TBPROT is programmed to 1, an

attempt to change it back to 0 will fail and set the Program Error bit (P_ERR in SR1[6]).

The desired state of TBPROT must be selected during the initial configuration of the device during system manufacture; before the

first program or erase operation on the main flash array. TBPROT must not be programmed after programming or erasing is done in

the main flash array.

CR1[4]: Reserved for Future Use

Block Protection Non-Volatile (BPNV) CR1[3]: The BPNV bit defines whether or not the BP2-0 bits in the Status Register are

volatile or non-volatile. The BPNV bit is OTP and cleared to a0 with the BP bits cleared to 000 when shipped from Cypress. When

BPNV is set to a 0 the BP2-0 bits in the Status Register are non-volatile. When BPNV is set to a 1 the BP2-0 bits in the Status

Register are volatile and will be reset to binary 111 after POR, hardware reset, or command reset. If BPNV is programmed to 1, an

attempt to change it back to 0 will fail and set the Program Error bit (P_ERR in SR1[6]).

TBPARM CR1[2]: TBPARM defines the logical location of the parameter block. The parameter block consists of thirty-two 4-kB

small sectors (SMS), which replace two 64-kB sectors. When TBPARM is set to a 1 the parameter block is in the top of the memory

array address space. When TBPARM is set to a 0 the parameter block is at the Bottom of the array. TBPARM is OTP and set to a 0

when it ships from Cypress. If TBPARM is programmed to 1, an attempt to change it back to 0 will fail and set the Program Error bit

(P_ERR in SR1[6]).

The desired state of TBPARM must be selected during the initial configuration of the device during system manufacture; before the

first program or erase operation on the main flash array. TBPARM must not be programmed after programming or erasing is done in

the main flash array.

TBPROT can be set or cleared independent of the TBPARM bit. Therefore, the user can elect to store parameter information from

the bottom of the array and protect boot code starting at the top of the array, and vice versa. Or the user can select to store and

protect the parameter information starting from the top or bottom together.

When the memory array is logically configured as uniform 256-kB sectors, the TBPARM bit is Reserved for Future Use (RFU) and

has no effect because all sectors are uniform size.

Quad Data Width (QUAD) CR1[1]: When set to 1, this bit switches the data width of the device to 4 bit - Quad mode. That is, WP#

becomes IO2 and HOLD# becomes IO3. The WP# and HOLD# inputs are not monitored for their normal functions and are internally

set to high (inactive). The commands for Serial, Dual Output, and Dual I/O Read still function normally but, there is no need to drive

WP# and Hold# inputs for those commands when switching between commands using different data path widths. The QUAD bit

must be set to one when using Read Quad Out, Quad I/O Read, Read DDR Quad I/O, and Quad Page Program commands. The

QUAD bit is non-volatile.

Freeze Protection (FREEZE) CR1[0]: The Freeze Bit, when set to 1, locks the current state of the BP2-0 bits in Status Register, the

TBPROT and TBPARM bits in the Configuration Register, and the OTP address space. This prevents writing, programming, or

erasing these areas. As long as the FREEZE bit remains cleared to logic 0 the other bits of the Configuration Register, including

FREEZE, are writable, and the OTP address space is programmable. Once the FREEZE bit has been written to a logic 1 it can only

be cleared to a logic 0 by a power-off to power-on cycle or a hardware reset. Software reset will not affect the state of the FREEZE

bit. The FREEZE bit is volatile and the default state of FREEZE after power-on is 0. The FREEZE bit can be set in parallel with

updating other values in CR1 by a single WRR command.

Document Number: 001-98283 Rev. *I

Page 52 of 144

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