S25FL256SDPMFVC03 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL256SDPMFVC03
Cypress Semiconductor
S25FL256SDPMFVC03 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
7.5.3
Status Register 2 (SR2)
Related Commands: Read Status Register 2 (RDSR2 07h).
Table 7.14 Status Register 2 (SR2)
Bits
Field Name
Function
Type
Default State
Description
7
RFU
Reserved
0
Reserved for Future Use
6
RFU
Reserved
0
Reserved for Future Use
5
RFU
Reserved
0
Reserved for Future Use
4
RFU
Reserved
0
Reserved for Future Use
3
RFU
Reserved
0
Reserved for Future Use
2
RFU
Reserved
0
Reserved for Future Use
1
ES
Erase Suspend
Volatile, Read only
0
1 = In erase suspend mode
0 = Not in erase suspend mode
0
PS
Program Suspend
Volatile, Read only
0
1 = In program suspend mode
0 = Not in program suspend mode
Erase Suspend (ES) SR2[1]: The Erase Suspend bit is used to determine when the device is in Erase Suspend mode. This is a
status bit that cannot be written. When Erase Suspend bit is set to 1, the device is in erase suspend mode. When Erase Suspend bit
is cleared to 0, the device is not in erase suspend mode. Refer to Erase Suspend and Resume Commands (75h) (7Ah) for details
about the Erase Suspend/Resume commands.
Program Suspend (PS) SR2[0]: The Program Suspend bit is used to determine when the device is in Program Suspend mode.
This is a status bit that cannot be written. When Program Suspend bit is set to 1, the device is in program suspend mode. When the
Program Suspend bit is cleared to 0, the device is not in program suspend mode. Refer to Program Suspend (PGSP 85h) and
Resume (PGRS 8Ah) on page 102 for details.
7.5.4
AutoBoot Register
Related Commands: AutoBoot Read (ABRD 14h) and AutoBoot Write (ABWR 15h).
The AutoBoot Register provides a means to automatically read boot code as part of the power-on reset, hardware reset, or software
reset process.
Table 7.15 AutoBoot Register
Bits
31 to 9
8 to 1
0
Field Name
ABSA
ABSD
ABE
Function
AutoBoot Start Address
AutoBoot Start Delay
AutoBoot Enable
Type
Non-Volatile
Non-Volatile
Non-Volatile
Default State
000000h
00h
0
Description
512 byte boundary address for the start of boot code
access
Number of initial delay cycles between CS# going low
and the first bit of boot code being transferred
1 = AutoBoot is enabled
0 = AutoBoot is not enabled
7.5.5
Bank Address Register
Related Commands: Bank Register Access (BRAC B9h), Write Register (WRR 01h), Bank Register Read (BRRD 16h) and Bank
Register Write (BRWR 17h).
The Bank Address register supplies additional high order bits of the main flash array byte boundary address for legacy commands
that supply only the low order 24 bits of address. The Bank Address is used as the high bits of address (above A23) for all 3-byte
address commands when EXTADD=0. The Bank Address is not used when EXTADD = 1 and traditional 3-byte address commands
are instead required to provide all four bytes of address.
Document Number: 001-98283 Rev. *I
Page 53 of 144
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