S25FL128S, S25FL256S
9.3.2
Read Status Register-2 (RDSR2 07h)
The Read Status Register (RDSR2) command allows the Status Register-2 contents to be read from SO. The Status Register-2
contents may be read at any time, even while a program, erase, or write operation is in progress. It is possible to read the Status
Register-2 continuously by providing multiples of eight clock cycles. The status is updated for each eight cycle read. The maximum
clock frequency for the RDSR2 command is 133 MHz.
Figure 9.5 Read Status Register-2 (RDSR2) Command
CS#
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction
7654321 0
High Impedance
Status Register-2 Out
7654321
MSB
Status Register-2 Out
0 765432 1
MSB
07
MSB
9.3.3
Read Configuration Register (RDCR 35h)
The Read Configuration Register (RDCR) command allows the Configuration Register contents to be read from SO. It is possible to
read the Configuration Register continuously by providing multiples of eight clock cycles. The Configuration Register contents may
be read at any time, even while a program, erase, or write operation is in progress.
CS#
SCK
SI
SO
Phase
Figure 9.6 Read Configuration Register (RDCR) Command Sequence
76543210
7 6 5 43 2 1 0 7 6 5 4 3 2 1 0
Instruction
Register Read
Repeat Register Read
9.3.4
Bank Register Read (BRRD 16h)
The Read the Bank Register (BRRD) command allows the Bank address Register contents to be read from SO. The instruction is
first shifted in from SI. Then the 8-bit Bank Register is shifted out on SO. It is possible to read the Bank Register continuously by
providing multiples of eight clock cycles. The maximum operating clock frequency for the BRRD command is 133 MHz.
Figure 9.7 Read Bank Register (BRRD) Command
CS#
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction
SI
7 65 4 3 2 1 0
MSB
Bank Register Out
Bank Register Out
High Impedance
SO
7 65 4 3 2 1 0 7 65 4 3 2 1 07
MSB
MSB
MSB
Document Number: 001-98283 Rev. *I
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