S25FL256SDPMFVC03 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL256SDPMFVC03
Cypress Semiconductor
S25FL256SDPMFVC03 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
9.3.16
Data Learning Pattern Read (DLPRD 41h)
The instruction is shifted on SI, then the 8-bit DLP is shifted out on SO. It is possible to read the DLP continuously by providing
multiples of eight clock cycles. The maximum operating clock frequency for the DLPRD command is 133 MHz.
Figure 9.21 DLP Read (DLPRD) Command Sequence
CS#
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction
Data Learning Pattern
Data Learning Pattern
SI
7654321 0
MSB
High Impedance
SO
765 43 2 1 0 765 43 2 1 0
MSB
MSB
9.4 Read Memory Array Commands
Read commands for the main flash array provide many options for prior generation SPI compatibility or enhanced performance SPI:
Some commands transfer address or data on each rising edge of SCK. These are called Single Data Rate commands (SDR).
Some SDR commands transfer address one bit per rising edge of SCK and return data 1, 2, or 4 bits of data per rising edge of
SCK. These are called Read or Fast Read for 1-bit data; Dual Output Read for 2-bit data, and Quad Output for 4-bit data.
Some SDR commands transfer both address and data 2 or 4 bits per rising edge of SCK. These are called Dual I/O for 2 bit
and Quad I/O for 4 bit.
Some commands transfer address and data on both the rising edge and falling edge of SCK. These are called Double Data
Rate (DDR) commands.
There are DDR commands for 1, 2, or 4 bits of address or data per SCK edge. These are called Fast DDR for 1-bit, Dual I/O
DDR for 2-bit, and Quad I/O DDR for 4-bit per edge transfer.
All of these commands begin with an instruction code that is transferred one bit per SCK rising edge. The instruction is followed by
either a 3- or 4-byte address transferred at SDR or DDR. Commands transferring address or data 2 or 4 bits per clock edge are
called Multiple I/O (MIO) commands. For FL-S devices at
256 Mbits or higher density, the traditional SPI 3-byte addresses are unable to directly address all locations in the memory array.
These device have a bank address register that is used with 3-byte address commands to supply the high order address bits beyond
the address from the host system. The default bank address is zero. Commands are provided to load and read the bank address
register. These devices may also be configured to take a 4-byte address from the host system with the traditional 3-byte address
commands. The 4-byte address mode for traditional commands is activated by setting the External Address (EXTADD) bit in the
bank address register to 1. In the FL128S, higher order address bits above A23 in the 4-byte address commands, commands using
Extended Address mode, and the Bank Address Register are not relevant and are ignored because the flash array is only 128 Mbits
in size.
The Quad I/O commands provide a performance improvement option controlled by mode bits that are sent following the address
bits. The mode bits indicate whether the command following the end of the current read will be another read of the same type,
without an instruction at the beginning of the read. These mode bits give the option to eliminate the instruction cycles when doing a
series of Quad I/O read accesses.
A device ordering option provides an enhanced high performance option by adding a similar mode bit scheme to the DDR Fast
Read, Dual I/O, and Dual I/O DDR commands, in addition to the Quad I/O command.
Document Number: 001-98283 Rev. *I
Page 82 of 144
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