S25FL256SDPMFVC03 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL256SDPMFVC03

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

Some commands require delay cycles following the address or mode bits to allow time to access the memory array. The delay

cycles are traditionally called dummy cycles. The dummy cycles are ignored by the memory thus any data provided by the host

during these cycles is “don’t care” and the host may also leave the SI signal at high impedance during the dummy cycles. When MIO

commands are used the host must stop driving the IO signals (outputs are high impedance) before the end of last dummy cycle.

When DDR commands are used the host must not drive the I/O signals during any dummy cycle. The number of dummy cycles

varies with the SCK frequency or performance option selected via the Configuration Register 1 (CR1) Latency Code (LC). Dummy

cycles are measured from SCK falling edge to next SCK falling edge. SPI outputs are traditionally driven to a new value on the falling

edge of each SCK. Zero dummy cycles means the returning data is driven by the memory on the same falling edge of SCK that the

host stops driving address or mode bits.

The DDR commands may optionally have an 8-edge Data Learning Pattern (DLP) driven by the memory, on all data outputs, in the

dummy cycles immediately before the start of data. The DLP can help the host memory controller determine the phase shift from

SCK to data edges so that the memory controller can capture data at the center of the data eye.

When using SDR I/O commands at higher SCK frequencies (>50 MHz), an LC that provides 1 or more dummy cycles should be

selected to allow additional time for the host to stop driving before the memory starts driving data, to minimize I/O driver conflict.

When using DDR I/O commands with the DLP enabled, an LC that provides 5 or more dummy cycles should be selected to allow 1

cycle of additional time for the host to stop driving before the memory starts driving the 4 cycle DLP.

Each read command ends when CS# is returned High at any point during data return. CS# must not be returned High during the

mode or dummy cycles before data returns as this may cause mode bits to be captured incorrectly; making it indeterminate as to

whether the device remains in enhanced high performance read mode.

9.4.1

Read (Read 03h or 4READ 13h)

The instruction

03h (ExtAdd=0) is followed by a 3-byte address (A23-A0) or

03h (ExtAdd=1) is followed by a 4-byte address (A31-A0) or

13h is followed by a 4-byte address (A31-A0)

Then the memory contents, at the address given, are shifted out on SO. The maximum operating clock frequency for the READ

command is 50 MHz.

The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address

in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read

instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back

to 000000h, allowing the read sequence to be continued indefinitely.

Figure 9.22 Read Command Sequence (3-byte Address, 03h [ExtAdd=0])

CS #

SCK

SI

SO

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

Instruction

High Impedance

24-Bit

Address

23 22 21

3210

76

MSB

DATA OUT 1

54321

DATA OUT 2

07

MSB

Document Number: 001-98283 Rev. *I

Page 83 of 144

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