S25FL256SDPMFVC03 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL256SDPMFVC03

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

CS#

SCK

SI

SO

Figure 9.26 Fast Read Command Sequence (4-byte Address, 0Ch or 0B [ExtAdd=1], LC=11b)

012345678

38 39 40 41 42 43 44 45 46 47 48 49

Instruction

32 Bit Address

7 6 5 4 3 2 1 0 31

10

Data 1

Data 2

7654321076

9.4.3

Dual Output Read (DOR 3Bh or 4DOR 3Ch)

The instruction

3Bh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or

3Bh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or

3Ch is followed by a 4-byte address (A31-A0)

Then the memory contents, at the address given, is shifted out two bits at a time through IO0 (SI) and IO1 (SO). Two bits are shifted

out at the SCK frequency by the falling edge of the SCK signal.

The maximum operating clock frequency for the Dual Output Read command is 104 MHz. For Dual Output Read commands, there

are zero or eight dummy cycles required after the last address bit is shifted into SI before data begins shifting out of IO0 and IO1.

This latency period (i.e., dummy cycles) allows the device’s internal circuitry enough time to read from the initial address. During the

dummy cycles, the data value on SI is a “don’t care” and may be high impedance. The number of dummy cycles is determined by the

frequency of SCK (refer to Table 7.12, Latency Codes for SDR Enhanced High Performance on page 51).

The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address

in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read

instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back

to 000000h, allowing the read sequence to be continued indefinitely.

Figure 9.27 Dual Output Read Command Sequence (3-byte Address, 3Bh [ExtAdd=0], LC=10b)

CS#

SCK

IO0

IO1

Phase

7 6 5 4 3 2 1 0 23 22 21 0

Instruction

Address

8 Dummy Cycles

6 42 06 42 0

7 53 17 53 1

Data 1

Data 2

Figure 9.28 Dual Output Read Command Sequence (4-byte Address, 3Ch or 3Bh [ExtAdd=1, LC=10b])

CS#

SCK

IO0

IO1

Phase

7 6 5 4 3 2 1 0 31 30 29 0

Instruction

Address

8 Dummy Cycles

6 42 06 42 0

7 53 17 53 1

Data 1

Data 2

Document Number: 001-98283 Rev. *I

Page 85 of 144

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