S25FL128SDPMHVB11 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL128SDPMHVB11
Cypress Semiconductor
S25FL128SDPMHVB11 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
Figure 9.42 Continuous DDR Fast Read Subsequent Access (3-byte Address [ExtAdd=0, EHPLC=11b])
CS#
0
11
12
13
14
15
16
17
18
19
20
21
SCK
12 cycles
24 Bit Address
4 cycles
Mode
1 cyc
Dummy
4 cycles
per data
IO0
23 22 1 0 7 6 5 4 3 2 1 0
IO1
7 654321076
Figure 9.43 DDR Fast Read Initial Access (4-byte Address, 0Eh or 0Dh [ExtAdd=1], EHPLC=01b)
CS#
0
1
2
3
4
5
6
7
8
23
24
25
26
27
28
29
30
31
32
33
34
35
36
SCK
8 cycles
Instruction
16 cycles
32b Add
4 cycles
Mode
4 cycles Dummy
Optional DLP
4 cycles
per data
SI
7
6
5
4
3
2
1
0
31 22 1 0 7 6 5 4 3 2 1 0
SO
7 65432107654321076
Note:
1. Example DLP of 34h (or 00110100).
Figure 9.44 Continuous DDR Fast Read Subsequent Access (4-byte Address [ExtAdd=1], EHPLC=01b)
CS#
0
15
16
17
18
19
20
21
22 23
24
25
26
27
28
SCK
16 cycles
32b Add
4 cycles
Mode
4 cycles Dummy
Optional DLP
4 cycles
per data
SI
31 22 1 0 7 6 5 4 3 2 1 0
SO
7 65432107654321076
Note:
1. Example DLP of 34h (or 00110100).
Figure 9.45 DDR Fast Read Subsequent Access (4-byte Address, HPLC=01b)
CS#
0 1 2 3 4 5 6 7 8 23 24 25 26 27 28 29 30 31 32 33 34
SCK
8 cycles
16 cycles
6 cycles
4 cycles
Instruction
32b Add
Dummy
per data
SI
7 6 5 4 3 2 1 0 31 22 1 0
SO
7654321076
Document Number: 001-98283 Rev. *I
Page 93 of 144
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