S25FL128SDPMHVB11 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL128SDPMHVB11
Cypress Semiconductor
S25FL128SDPMHVB11 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP of 34h. The DLP 34h
(or 00110100) will be driven on each of the active outputs (i.e. all four SIOs on a x4 device, both SIOs on a x2 device and the single
SO output on a x1 device). This pattern was chosen to cover both DC and AC data transition scenarios. The two DC transition
scenarios include data low for a long period of time (two half clocks) followed by a high going transition (001) and the complementary
low going transition (110). The two AC transition scenarios include data low for a short period of time (one half clock) followed by a
high going transition (101) and the complementary low going transition (010). The DC transitions will typically occur with a starting
point closer to the supply rail than the AC transitions that may not have fully settled to their steady state (DC) levels. In many cases
the DC transitions will bound the beginning of the data valid period and the AC transitions will bound the ending of the data valid
period. These transitions will allow the host controller to identify the beginning and ending of the valid data eye. Once the data eye
has been characterized the optimal data capture point can be chosen. See SPI DDR Data Learning Registers on page 55 for more
details.
Figure 9.49 DDR Quad I/O Read Initial Access (3-byte Address, EDh [ExtAdd=0], HPLC=11b)
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
8 cycles
Instruction
3 cycles
Address
1 cycle
Mode
3 cycle Dummy
High-Z Bus Turn-around
1 cycle per data
Data 0 Data 1
IO0
7
6
5
4
3
2
1
0
20 16 12 8 4 0 4 0
4 040
IO1
21 17 13 9 5 1 5 1
5 151
IO2
22 18 14 10 6 2 6 2
6 262
IO3
23 19 15 11 7 3 7 3
7 373
Figure 9.50 Continuous DDR Quad I/O Read Subsequent Access (3-byte Address,HPLC=11b)
CS#
0
1
2
3
4
5
6
7
8
SCK
3 cycle
A ddr es s
1 cycle
Mode
3 cycle Dummy
High-Z Bus Turn-around
1 cycle per data
Data 0
Data 1
IO0
20
16
12
8
4
0
4
0
4
0
4
0
IO1
21
17
13
9
5
1
5
1
5
1
5
1
IO2
22
18
14
10
6
2
6
2
6
2
6
2
IO3
23
19
15
11
7
3
7
3
7
3
7
3
Figure 9.51 DDR Quad I/O Read Initial Access (4-byte Address, EEh or EDh [ExtAdd=1], EHPLC=01b)
CS#
SCK
IO0
IO1
IO2
IO3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
8 cycles
Instruction
4 cycles
32 Bit Address
1 cycle
Mode
7 cycle Dummy
High-Z Bus Turn-around
Optional Data Learning Pattern
1 cycle per data
Data 0 Data 1
7
6
5
4
3
2
1
0
28 24 20 16 12 8 4 0 4 0
7 65432104040
29 25 21 17 13 9 5 1 5 1
7 65432105151
30 26 22 18 14 10 6 2 6 2
7 65432106262
31 27 23 19 15 11 7 3 7 3
7 65432107373
Note:
1. Example DLP of 34h (or 00110100).
Document Number: 001-98283 Rev. *I
Page 97 of 144
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