SWITCHING TEST WAVEFORMS
2.4 V
0.45 V
2.0 V
2.0 V
Test Points
0.8 V
0.8 V
Input
Output
3V
1.5 V
0V
Input
Test Points
1.5 V
Output
AC Testing (all speed options except -70): Inputs are driven at
2.4 V for a logic “1” and 0.45 V for a logic “0”. Input pulse rise
and fall times are ≤10 ns.
AC Testing for -70 devices: Inputs are driven at 3.0 V for a
logic “1” and 0 V for a logic “0”. Input pulse rise and fall times
are ≤10 ns.
11561G-15
SWITCHING CHARACTERISTICS over operating range unless otherwise specified
AC Characteristics—Read Only Operation
Parameter Symbols
Am28F512
JEDEC
Standard
Parameter Description
-70 -90 -120 -150 -200 Unit
tAVAV
tELQV
tAVQV
tGLQV
tELQX
tRC
Read Cycle Time (Note 2)
tCE
Chip Enable Access Time
tACC
Address Access Time
tOE
Output Enable Access Time
tLZ
Chip Enable to Output in Low Z
(Note 2)
Min
70
90 120 150 200 ns
Max 70 90 120 150 200 ns
Max 70 90 120 150 200 ns
Max
35
35
50
55
55
ns
Min
0
0
0
0
0
ns
tEHQZ
tDF
Chip Disable to Output in High Z
(Note 1)
Max
20
20
30
35
35
ns
tGLQX
tOLZ
Output Enable to Output in Low Z
(Note 2)
Min
0
0
0
0
0
ns
tGHQZ
tDF
Output Disable to Output in High Z
(Note 2)
Max 20
20
30
35
35
ns
tAXQX
tOH
Output Hold from first of Address,
CE#, or OE# Change (Note 2)
Min
0
0
0
0
0
ns
tWHGL
tVCS
Write Recovery Time before Read
VCC Setup Time to Valid Read
(Note 2)
Min
6
6
6
6
6
µs
Min
50
50
50
50
50
µs
Notes:
1. Guaranteed by design not tested.
2. Not 100% tested.
26
Am28F512