M48T212VMH View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M48T212VMH

3.3V TIMEKEEPER® supervisor

STMicroelectronics 

Clock operation

M48T212V

3

Clock operation

3.1

TIMEKEEPER® registers

The M48T212V offers 16 internal registers which contain TIMEKEEPER®, Alarm,

Watchdog, Flag, and Control data. These registers are memory locations which contain

external (user accessible) and internal copies of the data (usually referred to as BiPORT™

TIMEKEEPER cells).

The external copies are independent of internal functions except that they are updated

periodically by the simultaneous transfer of the incremented internal copy. TIMEKEEPER

and Alarm Registers store data in BCD. Control, Watchdog and Flags Registers store data

in Binary Format.

3.2

Reading the clock

Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent

reading data in transition. The BiPORT TIMEKEEPER cells in the RAM array are only data

registers and not the actual clock counters, so updating the registers can be halted without

disturbing the clock itself.

Updating is halted when a '1' is written to the READ Bit, D6 in the Control Register (8h). As

long as a '1' remains in that position, updating is halted. After a halt is issued, the registers

reflect the count; that is, the day, date, and time that were current at the moment the halt

command was issued.

All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an

update in progress. Updating occurs 1 second after the READ Bit is reset to a '0.'

3.3

Note:

Setting the clock

Bit D7 of the Control Register (8h) is the WRITE Bit. Setting the WRITE Bit to a '1,' like the

READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them with

the correct day, date, and time data in 24 hour BCD format (see Table 7 on page 18).

Resetting the WRITE Bit to a '0' then transfers the values of all time registers (Fh-9h, 1h) to

the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE

Bit is reset, the next clock update will occur one second later.

Upon power-up following a power failure, the READ Bit will automatically be set to a '1.' This

will prevent the clock from updating the TIMEKEEPER registers, and will allow the user to

read the exact time of the power-down event.

Resetting the READ Bit to a '0' will allow the clock to update these registers with the current

time. The WRITE Bit will be reset to a '0' upon power-up.

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