M48T212V
Clock operation
perform a software reset of the watchdog timer, the original time-out period can be written
into the Watchdog Register, effectively restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS Bit is programmed to output an interrupt,
a value of 00h needs to be written to the Watchdog Register in order to clear the IRQ/FT pin.
This will also disable the watchdog function until it is again programmed correctly. A READ
of the Flags Register will reset the Watchdog Flag (Bit D7; Register 0h).
The watchdog function is automatically disabled upon power-down and the Watchdog
Register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the
frequency test function is activated, the watchdog or alarm function prevails and the
frequency test function is denied.
3.7
3.8
Note:
VCC switch output
Vccsw output goes low when VOUT switches to VCC turning on a customer supplied P-
Channel MOSFET (see Figure 3 on page 8). The Motorola MTD20P06HDL is
recommended. This MOSFET in turn connects VOUT to a separate supply when the current
requirement is greater than IOUT1 (see Table 14 on page 28). This output may also be used
simply to indicate the status of the internal battery switchover comparator, which controls the
source (VCC or battery) of the VOUT output.
Power-on reset
The M48T212V continuously monitors VCC. When VCC falls to the power fail detect trip
point, the RST pulls low (open drain) and remains low on power-up for trec after VCC passes
VPFD (max). The RST pin is an open drain output and an appropriate pull-up resistor to VCC
should be chosen to control rise time.
If the RST output is fed back into either of the RSTIN inputs (for a microprocessor with a bi-
directional reset) then a 1kΩ (max) pull-up resistor is recommended.
3.9
Note:
Reset inputs (RSTIN1 & RSTIN2)
The M48T212V provides two independent inputs which can generate an output reset. The
duration and function of these resets is identical to a reset generated by a power cycle.
Table 9 and Figure 9 illustrate the AC reset characteristics of this function. During the time
RST is enabled (tR1HRH & tR2HRH), the Reset Inputs are ignored.
RSTIN1 and RSTIN2 are each internally pulled up to VCC through a 100KΩ resistor.
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