M48T212VMH View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M48T212VMH Datasheet PDF : 35 Pages
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Clock operation
Figure 9. (RSTIN1 & RSTIN2) timing waveforms
RSTIN1
tR1
RSTIN2
RST
tR2
tR1HRH
M48T212V
tR2HRH
AI02642
3.10
22/35
Table 9. Reset AC characteristics
Symbol
Parameter(1)
Min
Max
Unit
tR1(2)
tR2(3)
tR1HRH(4)
tR2HRH(4)
RSTIN1 low to RSTIN1 high
RSTIN2 low to RSTIN2 high
RSTIN1 high to RST high
RSTIN2 high to RST high
200
ns
100
ms
40
200
ms
40
200
ms
1. Valid for ambient operating temperature: TA = 0 to 70°C or –40 to 85°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V
(except where noted).
2. Pulse width less than 50ns will result in no RESET (for noise immunity).
3. Pulse width less than 20ms will result in no RESET (for noise immunity).
4. CL = 5pF (see Figure 13 on page 27).
Calibrating the clock
The M48T212V is driven by a quartz controlled oscillator with a nominal frequency of 32,768
Hz. The devices are tested not to exceed ±35 ppm (parts per million) oscillator frequency
error at 25°C, which equates to about ±1.53 minutes per month (see Figure 10 on page 24).
When the Calibration circuit is properly employed, accuracy improves to better than +1/–2
ppm at 25°C.
The oscillation rate of crystals changes with temperature. The M48T212V design employs
periodic counter correction. The calibration circuit adds or subtracts counts from the
oscillator divider circuit at the divide by 256 stage, as shown in Figure 11 on page 25. The
number of times pulses which are blanked (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five Calibration bits found in the
Control Register. Adding counts speeds the clock up, subtracting counts slows the clock
down.
The Calibration bits occupy the five lower-order bits (D4-D0) in the Control Register 8h.
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
Sign Bit; '1' indicates positive calibration, ‘0' indicates negative calibration. Calibration
occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened by 256 oscillator cycles.
If a binary ‘1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be
modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
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